公开(公告)号：US11978672B2

公开(公告)日：2024-05-07

申请号：US17885410

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/02263 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/823475 ,  H01L23/5226 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.

公开(公告)号：US20210257478A1

公开(公告)日：2021-08-19

申请号：US17306316

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US11094556B2

公开(公告)日：2021-08-17

申请号：US16383539

申请日：2019-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen Yeh ,  Yu-Tien Shen ,  Shih-Chun Huang ,  Po-Chin Chang ,  Wei-Liang Lin ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu

IPC: H01L21/3213 ,  H01L21/66

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

公开(公告)号：US10790195B2

公开(公告)日：2020-09-29

申请号：US16285052

申请日：2019-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L23/522

Abstract: A method includes following steps. A semiconductor fin is formed on a substrate and extends in a first direction. A source/drain region is formed on the semiconductor fin and a first interlayer dielectric (ILD) layer over the source/drain region. A gate stack is formed across the semiconductor fin and extends in a second direction substantially perpendicular to the first direction. A patterned mask having a first opening is formed over the first ILD layer. A protective layer is formed in the first opening using a deposition process having a faster deposition rate in the first direction than in the second direction. After forming the protective layer, the first opening is elongated in the second direction. A second opening is formed in the first ILD layer and under the elongated first opening. A conductive material is formed in the second opening.

公开(公告)号：US20190148147A1

公开(公告)日：2019-05-16

申请号：US16178417

申请日：2018-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun Huang ,  Chiu-Hsiang Chen ,  Ya-Wen Yeh ,  Yu-Tien Shen ,  Po-Chin Chang ,  Chien Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US12261082B2

公开(公告)日：2025-03-25

申请号：US17577707

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Lin-Yu Huang ,  Shuen-Shin Liang ,  Sheng-Tsung Wang ,  Cheng-Chi Chuang ,  Chia-Hung Chu ,  Tzu Pei Chen ,  Yuting Cheng ,  Sung-Li Wang

IPC: H01L21/768 ,  H01L23/535

Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

公开(公告)号：US20250022802A1

公开(公告)日：2025-01-16

申请号：US18221638

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tzu Pei Chen ,  Sung-Li Wang ,  Shin-Yi Yang ,  Po-Chin Chang ,  Yuting Cheng ,  Chia-Hung Chu ,  Chun-Hung Liao ,  Harry CHIEN ,  Chia-Hao Chang ,  Pinyen LIN

IPC: H01L23/535 ,  H01L21/768

Abstract: An integrated circuit (IC) with conductive structures and a method of fabricating the IC are disclosed. The method includes depositing a first dielectric layer on a semiconductor device, forming a conductive structure in the first dielectric layer, removing a portion of the first dielectric layer to expose a sidewall of the conductive structure, forming a barrier structure surrounding the sidewall of the conductive structure, depositing a conductive layer on the barrier structure, and performing a polishing process on the barrier structure and the conductive layer.

公开(公告)号：US12094951B1

公开(公告)日：2024-09-17

申请号：US18136493

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Ming-Huan Tsai ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

公开(公告)号：US12051620B2

公开(公告)日：2024-07-30

申请号：US17845891

申请日：2022-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Chang Sun ,  Po-Chin Chang ,  Akira Mineji ,  Zi-Wei Fang ,  Pinyen Lin

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088

CPC classification number: H01L21/76837 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/088

Abstract: A method for forming a semiconductor structure includes forming a gate structure on a substrate; depositing a first dielectric layer over the gate structure; depositing a second dielectric layer over the first dielectric layer and having a different density than the first dielectric layer; performing a first etching process on the first and second dielectric layers to form a trench; performing a second etching process on the first and second dielectric layers to modify the trench; filling a conductive material in the modified trench.

公开(公告)号：US12034059B2

公开(公告)日：2024-07-09

申请号：US18298095

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.