公开(公告)号：US20200335459A1

公开(公告)日：2020-10-22

申请号：US16916066

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chao-Wen Shih ,  Han-Ping Pu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

公开(公告)号：US10741508B2

公开(公告)日：2020-08-11

申请号：US15965995

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chao-Wen Shih ,  Han-Ping Pu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device including a chip package, a dielectric structure and a first antenna pattern is provided. The dielectric structure disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. A manufacturing method of a semiconductor device is also provided.

公开(公告)号：US20200020634A1

公开(公告)日：2020-01-16

申请号：US16035713

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Tsung Tsai ,  Ching-Hua Hsieh ,  Chih-Wei Lin ,  Sheng-Hsiang Chiu ,  Yi-Da Tsai

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065

Abstract: A package and a method of manufacturing the same are provided. The package includes a first die, a second die, a third die, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The third die is disposed on the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the third die and fills in a gap between the first die, the second die, and the third die. The RDL structure is disposed on the third die and the encapsulant.

公开(公告)号：US20190139787A1

公开(公告)日：2019-05-09

申请号：US15832742

申请日：2017-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Sheng-Hsiang Chiu ,  Yao-Tong Lai

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: An integrated fan-out (InFO) package includes at least one die, a plurality of conductive structures, an encapsulant, an enhancement layer, and a redistribution structure. The die has an active surface and includes a plurality of conductive posts on the active surface. The conductive structures surround the die. The encapsulant partially encapsulates the die. The enhancement layer is over the encapsulant. A top surface of the enhancement layer is substantially coplanar with top surfaces of the conductive posts and the conductive structures. A material of the enhancement layer is different from a material of the encapsulant. A roughness of an interface between the encapsulant and the enhancement layer is larger than a roughness of the top surface of the enhancement layer. The redistribution structure is over the enhancement layer and is electrically connected to the conductive structures and the die.

公开(公告)号：US10283470B2

公开(公告)日：2019-05-07

申请号：US15599480

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu ,  Sheng-Feng Weng

IPC: H01L23/28 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

公开(公告)号：US09859229B2

公开(公告)日：2018-01-02

申请号：US15227060

申请日：2016-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Peng Tsai ,  Sheng-Feng Weng ,  Sheng-Hsiang Chiu ,  Meng-Tse Chen ,  Chih-Wei Lin ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L25/065 ,  H01L23/552 ,  H01L25/00 ,  H01L23/60 ,  H05K9/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/60 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K9/0073 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a base layer. The package structure also includes a package layer encapsulating the integrated circuit die and the first shielding feature. The package structure further includes a second shielding feature extending from the side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature. The side surface of the second shielding feature faces away from the side surface of the base layer and is substantially coplanar with the side surface of the package layer.