公开(公告)号：US20170107100A1

公开(公告)日：2017-04-20

申请号：US15176365

申请日：2016-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Chih-Yu Wang ,  Hsi-Cheng Hsu ,  Hsin-Yu Chen ,  Ji-Hong Chiang ,  Jui-Chun Weng ,  Wei-Ding Wu

IPC: B81B7/00 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81B7/0041 ,  B81B3/0081 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/09 ,  B81C1/00293 ,  B81C2201/013 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/037 ,  B81C2203/038 ,  B81C2203/0735 ,  H01L28/20

Abstract: The present disclosure relates to a MEMs package having a heating element configured to adjust a pressure within a hermetically sealed chamber by inducing out-gassing of into the chamber, and an associated method. In some embodiments, the MEMs package has a CMOS substrate having one or more semiconductor devices arranged within a semiconductor body. A MEMs structure is connected to the CMOS substrate and has a micro-electromechanical (MEMs) device. The CMOS substrate and the MEMs structure form a hermetically sealed chamber abutting the MEMs device. A heating element is electrically coupled to the one or more semiconductor devices and is separated from the hermetically sealed chamber by an out-gassing layer arranged along an interior surface of the hermetically sealed chamber. By operating the heating element to cause the out-gassing layer to release a gas, the pressure of the hermetically sealed chamber can be adjusted after it is formed.

公开(公告)号：US10532925B2

公开(公告)日：2020-01-14

申请号：US16114521

申请日：2018-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Chih-Yu Wang ,  Hsi-Cheng Hsu ,  Hsin-Yu Chen ,  Ji-Hong Chiang ,  Jui-Chun Weng ,  Wei-Ding Wu

IPC: H01L49/02 ,  B81B7/00 ,  B81B3/00 ,  B81C1/00

Abstract: The present disclosure relates to a micro-electromechanical system (MEMs) package. In some embodiments, the MEMs package has a plurality of conductive interconnect layers disposed within a dielectric structure over an upper surface of a first substrate. A heating element is electrically coupled to a semiconductor device within the first substrate by one or more of the plurality of conductive interconnect layers. The heating element is vertically separated from the first substrate by the dielectric structure. A MEMs substrate is coupled to the first substrate and has a MEMs device. A hermetically sealed chamber surrounding the MEMs device is disposed between the first substrate and the MEMs substrate. An out-gassing material is disposed laterally between the hermetically sealed chamber and the heating element.

公开(公告)号：US10510671B2

公开(公告)日：2019-12-17

申请号：US15884760

申请日：2018-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cherng Jeng ,  Shyh-Wei Cheng ,  Yun Chang ,  Chen-Chieh Chiang ,  Jung-Chi Jeng

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The first mask layer has a trench. The trench has an inner wall and a bottom surface. The method includes forming a second mask layer in the trench. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The second trench exposes the bottom surface and is over a first portion of the dielectric layer. The remaining second mask layer covers the inner wall. The method includes removing the first portion, the first mask layer, and the second mask layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.

公开(公告)号：US10131536B2

公开(公告)日：2018-11-20

申请号：US15176365

申请日：2016-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Chih-Yu Wang ,  Hsi-Cheng Hsu ,  Hsin-Yu Chen ,  Ji-Hong Chiang ,  Jui-Chun Weng ,  Wei-Ding Wu

IPC: H01L29/84 ,  B81B7/00 ,  B81B3/00 ,  B81C1/00 ,  H01L49/02

Abstract: The present disclosure relates to a MEMs package having a heating element configured to adjust a pressure within a hermetically sealed chamber by inducing out-gassing of into the chamber, and an associated method. In some embodiments, the MEMs package has a CMOS substrate having one or more semiconductor devices arranged within a semiconductor body. A MEMs structure is connected to the CMOS substrate and has a micro-electromechanical (MEMs) device. The CMOS substrate and the MEMs structure form a hermetically sealed chamber abutting the MEMs device. A heating element is electrically coupled to the one or more semiconductor devices and is separated from the hermetically sealed chamber by an out-gassing layer arranged along an interior surface of the hermetically sealed chamber. By operating the heating element to cause the out-gassing layer to release a gas, the pressure of the hermetically sealed chamber can be adjusted after it is formed.

公开(公告)号：US09966427B2

公开(公告)日：2018-05-08

申请号：US15154027

申请日：2016-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Hung-Lin Chen ,  Jui-Chun Weng ,  Shiuan-Jeng Lin ,  Tian Sheng Lin ,  Yu-Jui Wu ,  Albion Pan ,  Bob Sun

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L28/75 ,  H01L21/31111 ,  H01L21/32139 ,  H01L23/5223

Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

公开(公告)号：US20170330931A1

公开(公告)日：2017-11-16

申请号：US15154027

申请日：2016-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Hung-Lin Chen ,  Jui-Chun Weng ,  Shiuan-Jeng Lin ,  Tian Sheng Lin ,  Yu-Jui Wu ,  Albion Pan ,  Bob Sun

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/522

CPC classification number: H01L28/75 ,  H01L21/31111 ,  H01L21/32139 ,  H01L23/5223

Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

公开(公告)号：US12157667B2

公开(公告)日：2024-12-03

申请号：US17719986

申请日：2022-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chun Weng ,  Lavanya Sanagavarapu ,  Ching-Hsiang Hu ,  Wei-Ding Wu ,  Shyh-Wei Cheng ,  Ji-Hong Chiang ,  Hsin-Yu Chen ,  Hsi-Cheng Hsu

IPC: B81B3/00 ,  B81C1/00 ,  H01J37/34 ,  H01L21/02

Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.

公开(公告)号：US11407636B2

公开(公告)日：2022-08-09

申请号：US16122180

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shyh-Wei Cheng ,  Chih-Yu Wang ,  Hsi-Cheng Hsu ,  Ji-Hong Chiang ,  Jui-Chun Weng ,  Shiuan-Jeng Lin ,  Wei-Ding Wu ,  Ching-Hsiang Hu

IPC: B81B7/00 ,  B81C1/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming a micro-electromechanical system (MEMS) package. The method includes forming one or more depressions within a capping substrate. A back-side of a MEMS substrate is bonded to the capping substrate after forming the one or more depressions, so that the one or more depressions define one or more cavities between the capping substrate and the MEMS substrate. A front-side of the MEMS substrate is selectively etched to form one or more trenches extending through the MEMS substrate, and one or more polysilicon vias are formed within the one or more trenches. A conductive bonding structure is formed on the front-side of the MEMS substrate at a location contacting the one or more polysilicon vias. The MEMS substrate is bonded to a CMOS substrate having one or more semiconductor devices by way of the conductive bonding structure.

公开(公告)号：US11305980B2

公开(公告)日：2022-04-19

申请号：US16717862

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chun Weng ,  Lavanya Sanagavarapu ,  Ching-Hsiang Hu ,  Wei-Ding Wu ,  Shyh-Wei Cheng ,  Ji-Hong Chiang ,  Hsin-Yu Chen ,  Hsi-Cheng Hsu

IPC: B81B3/00 ,  H01J37/34 ,  B81C1/00 ,  H01L21/02

Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.

公开(公告)号：US10770401B2

公开(公告)日：2020-09-08

申请号：US16715215

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cherng Jeng ,  Shyh-Wei Cheng ,  Yun Chang ,  Chen-Chieh Chiang ,  Jung-Chi Jeng

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first mask layer over a dielectric layer. The method includes forming a second mask layer over a first top surface of the first mask layer, the inner wall, and the bottom surface. The method includes removing the second mask layer covering the bottom surface to form a second trench in the second mask layer. The method includes forming an anti-bombardment layer over a second top surface of the second mask layer. The second mask layer and the anti-bombardment layer are made of different materials. The method includes removing the first portion, the first mask layer, the second mask layer, and the anti-bombardment layer to form a third trench in the dielectric layer. The method includes forming a conductive structure in the third trench.