公开(公告)号：US11742352B2

公开(公告)日：2023-08-29

申请号：US17826154

申请日：2022-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device includes first and second source/drain structures, a channel layer, a gate structure, and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on a first side surface of the channel layer. The epitaxial layer forms a P-N junction with a second side surface of the channel layer.

公开(公告)号：US11081592B2

公开(公告)日：2021-08-03

申请号：US16196329

申请日：2018-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Szu-Wei Huang ,  Hung-Li Chiang ,  Cheng-Hsien Wu ,  Chih Chieh Yeh

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/04 ,  H01L21/8238 ,  H01L27/04

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

公开(公告)号：US10522694B2

公开(公告)日：2019-12-31

申请号：US15719121

申请日：2017-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Szu-Wei Huang ,  Hung-Li Chiang ,  Cheng-Hsien Wu ,  Chih Chieh Yeh

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/04 ,  H01L21/8238 ,  H01L27/04

Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

公开(公告)号：US20190267292A1

公开(公告)日：2019-08-29

申请号：US16408877

申请日：2019-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Tung-Ying Lee ,  Szu-Wei Huang ,  Huan-Sheng Wei

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes first semiconductor wires over a semiconductor substrate. The first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure also includes a gate stack surrounding first portions of the first semiconductor wires, and a spacer element surrounding second portions of the first semiconductor wires. The first portions have a first width and the second portions have a second width. In addition, the semiconductor device structure includes a second semiconductor wire between the second portions. The second semiconductor wire has a third width, and the third width is substantially equal to the second width and greater than the first width.

公开(公告)号：US10290548B2

公开(公告)日：2019-05-14

申请号：US15692188

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Tung-Ying Lee ,  Szu-Wei Huang ,  Huan-Sheng Wei

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire.

公开(公告)号：US20180337094A1

公开(公告)日：2018-11-22

申请号：US16048581

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L27/088 ,  H01L21/306 ,  H01L29/06

CPC classification number: H01L21/823412 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US11177179B2

公开(公告)日：2021-11-16

申请号：US16914747

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  G03F1/38 ,  H01L21/308 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/08 ,  H01L29/78 ,  H01L29/775 ,  H01L29/417 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

公开(公告)号：US10699956B2

公开(公告)日：2020-06-30

申请号：US15800940

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  G03F1/38 ,  H01L21/308 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/08 ,  H01L29/78 ,  H01L29/775 ,  H01L29/417 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

公开(公告)号：US10290546B2

公开(公告)日：2019-05-14

申请号：US15666715

申请日：2017-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L29/49

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US20180151438A1

公开(公告)日：2018-05-31

申请号：US15666715

申请日：2017-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78651 ,  H01L29/78696

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.