公开(公告)号：US12211930B2

公开(公告)日：2025-01-28

申请号：US17403347

申请日：2021-08-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tse-An Chen ,  Lain-Jong Li ,  Wen-Hao Chang ,  Chien-Chih Tseng

IPC: H01L29/76 ,  H01L21/02 ,  H01L21/78 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

公开(公告)号：US20230360913A1

公开(公告)日：2023-11-09

申请号：US18356636

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ang Chao ,  Gregory Michael Pitner ,  Tse-An Chen ,  Lain-Jong Li ,  Yu Chao Lin

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10K10/84 ,  H10K10/46 ,  H10K71/00 ,  H10K71/12 ,  H10K85/20

CPC classification number: H01L21/02606 ,  H01L29/0669 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66045 ,  H01L29/78 ,  H01L29/7845 ,  H01L29/786 ,  H10K10/84 ,  H10K10/472 ,  H10K10/481 ,  H10K10/484 ,  H10K10/491 ,  H10K71/00 ,  H10K71/12 ,  H10K85/221

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

公开(公告)号：US11749528B2

公开(公告)日：2023-09-05

申请号：US17736505

申请日：2022-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ang Chao ,  Gregory Michael Pitner ,  Tse-An Chen ,  Lain-Jong Li ,  Yu Chao Lin

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10K10/84 ,  H10K10/46 ,  H10K71/00 ,  H10K71/12 ,  H10K85/20

CPC classification number: H01L21/02606 ,  H01L29/0669 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66045 ,  H01L29/78 ,  H01L29/786 ,  H01L29/7845 ,  H10K10/472 ,  H10K10/481 ,  H10K10/484 ,  H10K10/491 ,  H10K10/84 ,  H10K71/00 ,  H10K71/12 ,  H10K85/221

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

公开(公告)号：US11476356B2

公开(公告)日：2022-10-18

申请号：US16887729

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

公开(公告)号：US20210265501A1

公开(公告)日：2021-08-26

申请号：US16932268

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Lain-Jong Li ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L21/02 ,  H01L29/06

Abstract: In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.

公开(公告)号：US12224334B2

公开(公告)日：2025-02-11

申请号：US18324636

申请日：2023-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY ,  NATIONAL TAIWAN NORMAL UNIVERSITY

Inventor： Tung-Ying Lee ,  Tse-An Chen ,  Tzu-Chung Wang ,  Miin-Jang Chen ,  Yu-Tung Yin ,  Meng-Chien Yang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a plurality of semiconductor layers arranged one above another, and source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers. The semiconductor device further includes a gate structure surrounding each of the plurality of semiconductor layers. The gate structure includes interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer. The gate structure further includes gate spacers spacing apart the gate structure from the source/drain epitaxial regions. A top position of the high-k dielectric layer is lower than top positions of the gate spacers.

公开(公告)号：US12191144B2

公开(公告)日：2025-01-07

申请号：US17876487

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY ,  NATIONAL TAIWAN NORMAL UNIVERSITY

Inventor： Chun-Yi Chou ,  Po-Hsien Cheng ,  Tse-An Chen ,  Miin-Jang Chen

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.

公开(公告)号：US20220359737A1

公开(公告)日：2022-11-10

申请号：US17814620

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

公开(公告)号：US20220262635A1

公开(公告)日：2022-08-18

申请号：US17736505

申请日：2022-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Ang Chao ,  Gregory Michael Pitner ,  Tse-An Chen ,  Lain-Jong Li ,  Yu Chao Lin

IPC: H01L21/02 ,  H01L29/06 ,  H01L51/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L51/05 ,  H01L51/56 ,  H01L51/10 ,  H01L29/786

Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

公开(公告)号：US12033850B2

公开(公告)日：2024-07-09

申请号：US17991380

申请日：2022-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY ,  NATIONAL TAIWAN NORMAL UNIVERSITY

Inventor： Chun-Yi Chou ,  Po-Hsien Cheng ,  Tse-An Chen ,  Miin-Jang Chen

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/0228 ,  C23C16/042 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/76224 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.