公开(公告)号：US20230113294A1

公开(公告)日：2023-04-13

申请号：US18064910

申请日：2022-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/423 ,  H01L29/66

Abstract: A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.

公开(公告)号：US20210118793A1

公开(公告)日：2021-04-22

申请号：US17133264

申请日：2020-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L49/02 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively. A length of the first conductive segment is greater than a length of the third conductive segment.

公开(公告)号：US20210098453A1

公开(公告)日：2021-04-01

申请号：US17120839

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Li-Chun TIEN ,  Pin-Dai SUE ,  Wei-Cheng LIN

IPC: H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US20190096909A1

公开(公告)日：2019-03-28

申请号：US16022821

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Cheng-Chi CHUANG ,  Chih-Ming LAI ,  Chia-Tien WU ,  Charles Chew-Yuen YOUNG ,  Hui-Ting YANG ,  Jiann-Tyng TZENG ,  Ru-Gun LIU ,  Wei-Cheng LIN ,  Lei-Chun CHOU ,  Wei-An LAI

IPC: H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

公开(公告)号：US20180151567A1

公开(公告)日：2018-05-31

申请号：US15457640

申请日：2017-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng LIN ,  Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Charles Chew-Yuen YOUNG

IPC: H01L27/092 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/768

CPC classification number: H01L27/092 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807

Abstract: A semiconductor device includes an active region comprising a source/drain region and a plurality of poly strips spaced apart and arranged along a first direction crossing over the active region. The first direction is substantially perpendicular to a lengthwise direction of the active region. A first metal pattern is disposed on the poly strips and arranged along the first direction. A plurality of first interconnect plugs is interposed in between the poly strips and the first metal pattern and in between the active region and the first metal pattern. A position of the first interconnect plugs being variable along the first direction.

公开(公告)号：US20170256484A1

公开(公告)日：2017-09-07

申请号：US15058077

申请日：2016-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L29/423 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/762 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L28/00 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/01029

Abstract: A semiconductor structure is disclosed that includes a semiconductor structure includes an active area, a first conductive line, a conductive via, a first conductive metal segment coupled to the conductive line through the conductive via, a second conductive metal segment disposed over the active area, and a local conductive segment configured to couple the first conductive metal segment and the second conductive metal segment.

公开(公告)号：US20250167108A1

公开(公告)日：2025-05-22

申请号：US19030702

申请日：2025-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hung SHEN ,  Chih-Liang CHEN ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kam-Tou SIO ,  Wei-Cheng LIN

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H10D1/00 ,  H10D30/01 ,  H10D30/62 ,  H10D64/27 ,  H10D84/83 ,  H10D84/85 ,  H10D89/10

Abstract: A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.

公开(公告)号：US20240379554A1

公开(公告)日：2024-11-14

申请号：US18784733

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/522

Abstract: Apparatus and methods for back side routing a data signal in a semiconductor device are described. In one example, a described semiconductor cell structure includes: a dummy device region at a front side of the semiconductor cell structure; a metal layer including a plurality of metal lines at a back side of the semiconductor cell structure; a dielectric layer formed between the dummy device region and the metal layer; an inner metal disposed within the dielectric layer; at least one first via that is formed through the dielectric layer and electrically connects the inner metal to the plurality of metal lines at the back side; and at least one second via that is formed in the dielectric layer and physically coupled between the inner metal and the dummy device region at the front side.

公开(公告)号：US20220336354A1

公开(公告)日：2022-10-20

申请号：US17230856

申请日：2021-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/48

Abstract: Apparatus and methods for back side routing a data signal in a semiconductor device are described. In one example, a described semiconductor cell structure includes: a dummy device region at a front side of the semiconductor cell structure; a metal layer including a plurality of metal lines at a back side of the semiconductor cell structure; a dielectric layer formed between the dummy device region and the metal layer; an inner metal disposed within the dielectric layer; at least one first via that is formed through the dielectric layer and electrically connects the inner metal to the plurality of metal lines at the back side; and at least one second via that is formed in the dielectric layer and physically coupled between the inner metal and the dummy device region at the front side.

公开(公告)号：US20220254688A1

公开(公告)日：2022-08-11

申请号：US17730801

申请日：2022-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Wei PENG ,  Wei-Cheng LIN ,  Jiann-Tyng TZENG

IPC: H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor comprises a first source/drain, a second source/drain, and a first gate between the first and second source/drains, and the second transistor comprises a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains; forming an isolation layer to cover the second source/drain of the first transistor; and forming a first source/drain contact on and in contact the fourth source/drain of the second transistor and the isolation layer.