公开(公告)号：US20170287779A1

公开(公告)日：2017-10-05

申请号：US15628267

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsien Huang ,  Hong-Mao Lee ,  Hsien-Lung Yang ,  Yu-Kai Chen ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L21/8238

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

公开(公告)号：US20240413020A1

公开(公告)日：2024-12-12

申请号：US18488393

申请日：2023-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Chun-I Tsai ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Syun-Ming Jang ,  Wei-Jen Lo ,  Wei-Jung Lin ,  Yu-Ting Wen ,  Kai-Chieh Yang

IPC: H01L21/8238 ,  H01L21/321 ,  H01L27/092 ,  H01L29/66

Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.

公开(公告)号：US20240387265A1

公开(公告)日：2024-11-21

申请号：US18786535

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chang-Ting Chung ,  Yi-Hsiang Chao ,  Yu-Ting Wen ,  Kai-Chieh Yang ,  Yu-Chen Ko ,  Peng-Hao Hsu ,  Ya-Yi Cheng ,  Min-Hsiu Hung ,  Chun-Hsien Huang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/535

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

公开(公告)号：US12148659B2

公开(公告)日：2024-11-19

申请号：US18308743

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Yu Chang ,  Chun-I Tsai ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/8234 ,  H01L29/66

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

公开(公告)号：US20230268228A1

公开(公告)日：2023-08-24

申请号：US18308743

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Yu Chang ,  Chun-I Tsai ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67

CPC classification number: H01L21/76846 ,  H01L21/67075 ,  H01L21/76877 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/66545

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

公开(公告)号：US20230260836A1

公开(公告)日：2023-08-17

申请号：US17663315

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei Shan Chang ,  Yi-Hsiang Chao ,  Chun-Hsien Huang ,  Peng-Hao Hsu ,  Kevin Lee ,  Shu-Lan Chang ,  Ya-Yi Cheng ,  Ching-Yi Chen ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/76852 ,  H01L29/78618 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823418 ,  H01L21/76876

Abstract: A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

公开(公告)号：US11532561B2

公开(公告)日：2022-12-20

申请号：US16984884

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC: H01L23/535 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/285 ,  H01L23/48

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US20220352020A1

公开(公告)日：2022-11-03

申请号：US17809922

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsien Huang ,  I-Li Chen ,  Pin-Wen Chen ,  Yuan-Chen Hsu ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening

公开(公告)号：US20220148920A1

公开(公告)日：2022-05-12

申请号：US17580904

申请日：2022-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsien Huang ,  Hong-Mao Lee ,  Hsien-Lung Yang ,  Yu-Kai Chen ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

公开(公告)号：US11232985B2

公开(公告)日：2022-01-25

申请号：US16571536

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsien Huang ,  Hong-Mao Lee ,  Hsien-Lung Yang ,  Yu-Kai Chen ,  Wei-Jung Lin

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.