公开(公告)号：US20240387198A1

公开(公告)日：2024-11-21

申请号：US18786739

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu ,  Weiming Chris Chen

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538

Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

公开(公告)号：US20240385377A1

公开(公告)日：2024-11-21

申请号：US18786787

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Chen-Hua Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: G02B6/13 ,  G02B6/12 ,  G02B6/124

Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

公开(公告)号：US20240329302A1

公开(公告)日：2024-10-03

申请号：US18741308

申请日：2024-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Jiun Yi Wu ,  Hung-Yi Kuo ,  Shang-Yun Hou

IPC: G02B6/12 ,  H01L23/00 ,  H01L25/16 ,  H01L25/18 ,  H01L31/02 ,  H01L31/0232

CPC classification number: G02B6/12004 ,  H01L24/19 ,  H01L24/20 ,  H01L25/167 ,  H01L25/18 ,  H01L31/02002 ,  H01L31/02327 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/211 ,  H01L2224/32145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

公开(公告)号：US12038599B2

公开(公告)日：2024-07-16

申请号：US17340363

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Jiun Yi Wu ,  Hung-Yi Kuo ,  Shang-Yun Hou

IPC: G02B6/12 ,  H01L23/00 ,  H01L25/16 ,  H01L25/18 ,  H01L31/02 ,  H01L31/0232

CPC classification number: G02B6/12004 ,  H01L24/19 ,  H01L24/20 ,  H01L25/167 ,  H01L25/18 ,  H01L31/02002 ,  H01L31/02327 ,  H01L24/08 ,  H01L24/32 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/211 ,  H01L2224/32145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.

公开(公告)号：US20240103220A1

公开(公告)日：2024-03-28

申请号：US18526706

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/122

CPC classification number: G02B6/1225 ,  G02B6/12019

Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

公开(公告)号：US20230393336A1

公开(公告)日：2023-12-07

申请号：US18358749

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Chen-Hua Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: G02B6/13 ,  G02B6/12 ,  G02B6/124

CPC classification number: G02B6/13 ,  G02B6/12002 ,  G02B6/124 ,  G02B2006/12107

Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

公开(公告)号：US20220381985A1

公开(公告)日：2022-12-01

申请号：US17818845

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Chen-Hua Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: G02B6/13 ,  G02B6/124 ,  G02B6/12

Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

公开(公告)号：US11508737B2

公开(公告)日：2022-11-22

申请号：US16910498

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L27/11 ,  H01L27/11582 ,  H01L49/02 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US11164855B2

公开(公告)日：2021-11-02

申请号：US16572619

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Chi-Hsi Wu ,  Chih-Wei Wu ,  Kuo-Chiang Ting ,  Szu-Wei Lu ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Hsien-Ju Tsou ,  Cheng-Chieh Li

IPC: H01L23/32 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56 ,  H01L23/367

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

公开(公告)号：US20210132310A1

公开(公告)日：2021-05-06

申请号：US17121060

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/42 ,  H01L23/00

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.