公开(公告)号：US11282750B2

公开(公告)日：2022-03-22

申请号：US17010995

申请日：2020-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan Hsuan Hsu ,  I-Hsiu Wang ,  Yean-Zhaw Chen ,  Cheng-Wei Chang ,  Yu Shih Wang ,  Hsin-Yan Lu ,  Yi-Wei Chiu

IPC: H01L21/8234 ,  H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L27/02 ,  H01L29/08 ,  H01L27/088

Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.

公开(公告)号：US11276571B2

公开(公告)日：2022-03-15

申请号：US16907634

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Hong-Jie Yang ,  Chia-Ying Lee ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/027 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

公开(公告)号：US20210375677A1

公开(公告)日：2021-12-02

申请号：US16887316

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu Shih Wang ,  Kuo-Bin Huang ,  Ming-Hsi Yeh ,  Po-Nan Yeh

IPC: H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L23/535

Abstract: A method for forming a semiconductor device includes forming a metal contact on a substrate, forming a first dielectric on the metal contact, forming a first opening in the first dielectric, and performing a wet etch on a bottom surface of the first opening through a first etch stop layer (ESL) over the metal contact. The wet etch forms a first recess in a top surface of the metal contact. An upper width of the first recess is smaller than a lower width of the first recess. A first conductive feature is formed in the first recess and the first opening.

公开(公告)号：US20210134662A1

公开(公告)日：2021-05-06

申请号：US17120668

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Shian Wei Mao ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522

Abstract: In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

公开(公告)号：US12020981B2

公开(公告)日：2024-06-25

申请号：US18359036

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Chun-I Tsai ,  Shian Wei Mao ,  Ken-Yu Chang ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L23/48 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76847 ,  H01L21/32134 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

公开(公告)号：US11195752B1

公开(公告)日：2021-12-07

申请号：US16887316

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu Shih Wang ,  Kuo-Bin Huang ,  Ming-Hsi Yeh ,  Po-Nan Yeh

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/3213 ,  H01L23/535 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49

Abstract: A method for forming a semiconductor device includes forming a metal contact on a substrate, forming a first dielectric on the metal contact, forming a first opening in the first dielectric, and performing a wet etch on a bottom surface of the first opening through a first etch stop layer (ESL) over the metal contact. The wet etch forms a first recess in a top surface of the metal contact. An upper width of the first recess is smaller than a lower width of the first recess. A first conductive feature is formed in the first recess and the first opening.

公开(公告)号：US20210225701A1

公开(公告)日：2021-07-22

申请号：US17221958

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Chun-I Tsai ,  Shian Wei Mao ,  Ken-Yu Chang ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/485

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

公开(公告)号：US20210202238A1

公开(公告)日：2021-07-01

申请号：US16907634

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Hong-Jie Yang ,  Chia-Ying Lee ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/027 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L29/78

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

公开(公告)号：US20210134660A1

公开(公告)日：2021-05-06

申请号：US16906615

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US10361120B2

公开(公告)日：2019-07-23

申请号：US15880448

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Chun-I Tsai ,  Shian Wei Mao ,  Ken-Yu Chang ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L21/3213

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.