中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

53 records (took 0.026 seconds)

    Capacitor structure with low capacitance
    11.
    发明授权
    Capacitor structure with low capacitance 有权

    公开(公告)号：US11670672B2

    公开(公告)日：2023-06-06

    申请号：US17306796

    申请日：2021-05-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-Yi Chen ,  Chung-Chieh Yang ,  Yung-Chow Peng

    IPC: H01L23/522 ,  H01L49/02

    CPC classification number: H01L28/60 ,  H01L23/5223

    Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

    CAPACITOR STRUCTURE WITH LOW CAPACITANCE
    14.
    发明申请
    CAPACITOR STRUCTURE WITH LOW CAPACITANCE 审中-公开

    公开(公告)号：US20200227516A1

    公开(公告)日：2020-07-16

    申请号：US16834265

    申请日：2020-03-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-Yi Chen ,  Chung-Chieh Yang ,  Yung-Chow Peng

    IPC: H01L49/02 ,  H01L23/522

    Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

    3D thermal detection circuits and methods
    15.
    发明授权
    3D thermal detection circuits and methods 有权

    公开(公告)号：US10274380B2

    公开(公告)日：2019-04-30

    申请号：US15460098

    申请日：2017-03-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Szu-Lin Liu ,  Jaw-Juinn Horng ,  Yung-Chow Peng

    IPC: B41J2/38 ,  G01K7/21 ,  G01K7/20

    Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

    IC degradation management circuit, system and method
    16.
    发明授权
    IC degradation management circuit, system and method 有权

    公开(公告)号：US10222412B2

    公开(公告)日：2019-03-05

    申请号：US15170707

    申请日：2016-06-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Zeng Kang ,  Chih-Hsien Chang ,  Wen-Shen Chou ,  Yung-Chow Peng

    IPC: G06F17/50 ,  G01R31/28 ,  H03K3/03 ,  H03K19/20

    Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

    3D thermal detection circuits and methods
    18.
    发明授权
    3D thermal detection circuits and methods 有权

    公开(公告)号：US09599517B2

    公开(公告)日：2017-03-21

    申请号：US14055909

    申请日：2013-10-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Szu-Lin Liu ,  Jaw-Juinn Horng ,  Yung-Chow Peng

    IPC: G01K7/00 ,  G01K7/21 ,  G01K7/20

    CPC classification number: G01K7/21 ,  G01K7/20

    Abstract: A circuit includes sensing circuitry including at least one sensing element configured to output at least one temperature-dependent voltage. A compare circuit is configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage. A control circuit is configured to generate at least one control signal in response to the intermediate voltage. A switching circuit is configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal having a pulse width that is based on a temperature sensed by the sensing circuitry.

    Integrated Circuit With Transistor Array And Layout Method Thereof
    19.
    发明申请
    Integrated Circuit With Transistor Array And Layout Method Thereof 有权
    具有晶体管阵列的集成电路及其布局方法

    公开(公告)号：US20160266597A1

    公开(公告)日：2016-09-15

    申请号：US15161585

    申请日：2016-05-23

    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

    Inventor： Ching-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

    IPC: G05F3/26 ,  H01L27/07 ,  G06F17/50 ,  H01L27/06

    CPC classification number: G05F3/262 ,  G06F17/5072 ,  H01L27/0617 ,  H01L27/0705 ,  H01L27/10 ,  H01L29/42376

    Abstract: A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K

    Abstract translation: 电流镜电路包括第一电流镜腿和第二电流镜腿。 第一电流镜腿配置有N级第一晶体管串联耦合，并且其各自的栅极连接在一起。 第二电流镜腿配置有N级第二晶体管，其串联耦合并且其各自的栅极连接在一起。 第一晶体管和第二晶体管被实现在晶体管阵列内，第一晶体管和第二晶体管耦合在第一参考端和第二参考端之间，第一晶体管和第二晶体管在与第一晶体管和第二晶体管相邻的第一至第K级 参考端子实现在晶体管阵列的角区域，N和K是正整数，K

    In Situ on the Fly On-Chip Variation Measurement
    20.
    发明申请
    In Situ on the Fly On-Chip Variation Measurement 有权
    在现场的片上变化测量

    公开(公告)号：US20150177327A1

    公开(公告)日：2015-06-25

    申请号：US14134259

    申请日：2013-12-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jinn-Yeh Chien ,  Yung-Chow Peng ,  Chung-Chieh Yang ,  Kuan-Yu Lin

    IPC: G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/31727 ,  G01R31/31718 ,  G01R31/31725

    Abstract: A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

    Abstract translation: 提供集成电路设计的方法和电路。 提供了用于集成电路的第一电子设计文件。 该集成电路的第一电子设计文件具有定时测量电路。 基于第一个电子设计文件，制造了许多集成电路。 这些制造的集成电路具有布置在其上的预定位置的各自的定时测量电路。 定时测量电路用于在集成电路上测量受制造变化的各个定时延迟值的数量。 测量的定时延迟值用于设置自动放置和布线工具如何在第二个电子设计文件中排列块，该第二个电子设计文件在测量定时延迟值之后被路由，以考虑任何测量的制造变化。

Patent Agency Ranking