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    Stacked semiconductor devices and methods of forming same
    14.
    发明授权
    Stacked semiconductor devices and methods of forming same 有权

    公开(公告)号：US11430670B2

    公开(公告)日：2022-08-30

    申请号：US17101608

    申请日：2020-11-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsien-Wei Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

    Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    16.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220013461A1

    公开(公告)日：2022-01-13

    申请号：US16924201

    申请日：2020-07-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Hung Lin ,  An-Jhih Su ,  Der-Chyang Yeh ,  Shih-Guo Shen ,  Chia-Nan Yuan ,  Ming-Shih Yeh

    IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

    Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.

    Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method
    19.
    发明申请
    Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method 有权

    公开(公告)号：US20210305086A1

    公开(公告)日：2021-09-30

    申请号：US17346559

    申请日：2021-06-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Der-Chyang Yeh

    IPC: H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

    Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

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