公开(公告)号：US06686274B1

公开(公告)日：2004-02-03

申请号：US09787743

申请日：2001-06-08

申请人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shuji Ikeda

发明人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shuji Ikeda

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76877

摘要： In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.

摘要翻译： 在具有钴硅化物膜的半导体器件中，钴硅化物膜中至少含有镍或铁，以防止附着于薄膜变薄的电阻上升。

公开(公告)号：US06521932B1

公开(公告)日：2003-02-18

申请号：US09525029

申请日：2000-03-14

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

IPC分类号： H01L27108

CPC分类号： H01L21/7687 ,  H01L23/53238 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

公开(公告)号：US06639263B2

公开(公告)日：2003-10-28

申请号：US10255714

申请日：2002-09-27

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

IPC分类号： H01L27108

CPC分类号： H01L21/7687 ,  H01L23/53238 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

摘要翻译： 本发明的目的是提供一种具有存储电容器和使用铜作为主导电膜的布线的高可靠性半导体器件。 根据上述目的，本发明提供一种半导体器件，包括：半导体衬底; 形成在所述半导体基板的所述主面侧的作为第一电极的保持电容器和布置成放置电容器绝缘膜的第二电极; 形成在所述半导体衬底的主表面侧并且包括所述铜（Cu）元件的布线导体; 以及形成在所述布线导体的表面上的第一膜; 其中构成第一膜的材料和构成第一电极和/或第二电极的材料包括相同的元件。

公开(公告)号：US20060214254A1

公开(公告)日：2006-09-28

申请号：US11443226

申请日：2006-05-31

申请人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

发明人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

IPC分类号： H01L29/00

CPC分类号： H01L27/11526 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546

摘要： To suppress occurrence of defects in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

摘要翻译： 为了抑制半导体衬底中的缺陷的发生，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面 定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

公开(公告)号：US06965140B2

公开(公告)日：2005-11-15

申请号：US10669330

申请日：2003-09-25

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/52 ,  H01L23/532 ,  H01L27/00 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/7687 ,  H01L23/53238 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

摘要翻译： 本发明的目的是提供一种具有存储电容器和使用铜作为主导电膜的布线的高可靠性半导体器件。 根据上述目的，本发明提供一种半导体器件，包括：半导体衬底; 形成在所述半导体基板的所述主面侧的作为第一电极的保持电容器和布置成放置电容器绝缘膜的第二电极; 形成在所述半导体衬底的主表面侧并且包括所述铜（Cu）元件的布线导体; 以及形成在所述布线导体的表面上的第一膜; 其中构成第一膜的材料和构成第一电极和/或第二电极的材料包括相同的元件。

公开(公告)号：US06468845B1

公开(公告)日：2002-10-22

申请号：US09536642

申请日：2000-03-28

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L2184

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 例如，通过氧化硅膜5在半导体衬底4上的氧化硅膜5上形成电极2时，栅电极2被构成为多个多晶硅层6的层叠结构。栅极部分 通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成电极2。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

公开(公告)号：US5444302A

公开(公告)日：1995-08-22

申请号：US168506

申请日：1993-12-22

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L29/49 ,  H01L23/48 ,  H01L29/46

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004

摘要： In forming an electrode 2 on a silicon 6 oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 例如，通过氧化硅膜5在半导体衬底4上的硅6氧化膜5上形成电极2时，栅电极2被构成为多个多晶硅层6的层叠结构。 通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成栅电极2。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

公开(公告)号：US07442593B2

公开(公告)日：2008-10-28

申请号：US11480912

申请日：2006-07-06

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 在半导体衬底4上的氧化硅膜5上通过氧化硅膜5形成电极2时，例如，栅电极2被构成为多个多晶硅层6的叠层结构。 栅电极2的部分通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

公开(公告)号：US07091520B2

公开(公告)日：2006-08-15

申请号：US10265105

申请日：2002-10-07

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L29/10

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 在半导体衬底4上的氧化硅膜5上通过氧化硅膜5形成电极2时，例如，栅电极2被构成为多个多晶硅层6的叠层结构。 栅电极2的部分通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

公开(公告)号：US06346731B1

公开(公告)日：2002-02-12

申请号：US09499898

申请日：2000-02-08

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H02L2976

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 例如，通过氧化硅膜5在半导体衬底4上的氧化硅膜5上形成电极2时，栅电极2被构成为多个多晶硅层6的层叠结构。栅极部分 通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成电极2。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。