公开(公告)号：US4384248A

公开(公告)日：1983-05-17

申请号：US160174

申请日：1980-06-17

Applicant: Yasuo Matsuda ,  Kazuo Honda ,  Takeo Maeda

Inventor： Yasuo Matsuda ,  Kazuo Honda ,  Takeo Maeda

IPC: G01R31/02 ,  H02H7/122 ,  H02H3/28

CPC classification number: G01R31/025 ,  H02H7/1225

Abstract: Shortcircuit in an arm including a series connection of GTO's and reactors of an inverter is detected by sensing a voltage across the reactor. In one method, the shortcircuit in the arm is detected when voltages are coincidently applied to a P-line arm reactor and an N-line arm reactor for a predetermined time period. In another method, it is detected when an integrated value of a voltage across at least one of the reactors exceeds a predetermined level.

Abstract translation: 通过感测反应堆两端的电压来检测包括GTO和逆变器的反应器的串联连接的臂中的短路。 在一种方法中，当预定时间段内的电压一致地施加到P线臂式电抗器和N型臂式电抗器时，检测到臂中的短路。 在另一种方法中，当跨过至少一个电抗器的电压的积分值超过预定电平时检测。

公开(公告)号：US5523242A

公开(公告)日：1996-06-04

申请号：US243919

申请日：1994-05-17

Applicant: Takeo Maeda ,  Hiroshi Momose

Inventor： Takeo Maeda ,  Hiroshi Momose

IPC: H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/009

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a source drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Abstract translation: 一种制造半导体器件的方法。 制备半导体衬底，并且在半导体衬底的表面上形成栅极氧化膜。 选择性地去除栅极氧化膜以暴露半导体衬底的部分，并且在所得半导体结构上形成第一多晶硅层。 将杂质注入多晶硅层，并将所得半导体结构退火以活化杂质。 图案化第一多晶硅层以形成双极晶体管的基极和MOS晶体管的源极漏极。 然后在所得半导体结构上形成绝缘层。 然后选择性地暴露半导体衬底的部分，并且在所得半导体结构上形成第二多晶硅层。 然后将第二多晶硅层图案化以形成双极晶体管的发射极。

公开(公告)号：US5506168A

公开(公告)日：1996-04-09

申请号：US321132

申请日：1994-10-11

Applicant: Shigeru Morita ,  Fumitomo Matsuoka ,  Hisao Yoshimura ,  Takeo Maeda

Inventor： Shigeru Morita ,  Fumitomo Matsuoka ,  Hisao Yoshimura ,  Takeo Maeda

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76237 ,  Y10S438/978

Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface or the projecting portion in a slope shape, which is from the top portion of the projecting portion to the main surface.

Abstract translation: 本发明的半导体器件的制造方法具有在半导体基板的主面上形成绝缘材料的工序。 形成从材料膜的表面延伸到基底的凹槽。 凹槽用第一绝缘膜掩埋。 通过使用第一绝缘膜作为蚀刻掩模，去除材料膜，从而可以获得从主表面突出到第一绝缘膜的突出部分。 第二绝缘膜形成在从突出部分的顶部到主表面的倾斜形状的侧面或突出部分上。

公开(公告)号：US5406115A

公开(公告)日：1995-04-11

申请号：US52919

申请日：1993-04-27

Applicant: Takeo Maeda ,  Hiroshi Gojohbori ,  Yoshitaka Tsunashima

Inventor： Takeo Maeda ,  Hiroshi Gojohbori ,  Yoshitaka Tsunashima

IPC: H01L29/73 ,  H01L21/331 ,  H01L27/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/72 ,  H01L27/02

CPC classification number: H01L29/7322 ,  H01L27/0623 ,  H01L29/1004

Abstract: A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

Abstract translation: 本发明的半导体器件包括用作双极晶体管的集电极的N型半导体区域，掺杂有硼并与N型半导体区域的表面接触形成的二氧化硅膜，P型半导体区域 形成为与N型半导体区域中掺杂有硼的二氧化硅膜接触并用作双极晶体管的基极，并且形成在P型半导体区域中并用作发光体的N型半导体区域 双极晶体管。

公开(公告)号：US5278099A

公开(公告)日：1994-01-11

申请号：US976664

申请日：1992-11-16

Applicant: Takeo Maeda

Inventor： Takeo Maeda

IPC: H01L23/532 ,  H01L29/45 ,  H01L21/44

CPC classification number: H01L23/53223 ,  H01L29/456 ,  H01L2924/0002

Abstract: A semiconductor device of the invention has a p.sup.+ -type silicon source region, an insulating film formed on the source region and having a contact hole, and a wiring electrode connected to the source region through the contact hole. The wiring electrode has a Ti layer formed on the insulating film and an exposed surface of the source region, a TiN layer formed on the Ti layer, and an Al layer formed on the TiN layer.

Abstract translation: 本发明的半导体器件具有p +型硅源区域，形成在源极区上并具有接触孔的绝缘膜，以及通过接触孔与源极区域连接的布线电极。 布线电极具有形成在绝缘膜上的Ti层和源极区域的暴露表面，形成在Ti层上的TiN层和在TiN层上形成的Al层。

公开(公告)号：US5091760A

公开(公告)日：1992-02-25

申请号：US507037

申请日：1990-04-10

Applicant: Takeo Maeda ,  Hiroshi Momose

Inventor： Takeo Maeda ,  Hiroshi Momose

IPC: H01L21/285 ,  H01L21/331 ,  H01L21/8249

CPC classification number: H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/009

Abstract: A semiconductor device includes a semiconductor substrate, a bipolar transistor and a MOS transistor. The bipolar transistor is formed on the semiconductor substrate and has electrodes. A base electrode of the bipolar transistor and the electrodes of the MOS transistor contain the same kind of impurity so as to form a single layer.

Abstract translation: 半导体器件包括半导体衬底，双极晶体管和MOS晶体管。 双极晶体管形成在半导体衬底上并具有电极。 双极晶体管的基极和MOS晶体管的电极含有相同种类的杂质以形成单层。

公开(公告)号：US4931407A

公开(公告)日：1990-06-05

申请号：US211010

申请日：1988-06-24

Applicant: Takeo Maeda ,  Koji Makita

Inventor： Takeo Maeda ,  Koji Makita

IPC: H01L21/8249

CPC classification number: H01L21/8249

Abstract: A method for manufacturing MOS and bipolar transistors is proposed which includes MOS and bipolar transistors. The method comprises implanting impurity ions in a channel formation region with a dummy gate insulating film interposed and, subsequent to forming a gate oxide film on the surface of the resultant structure, impurity ions are implanted into an internal base region of the bipolar transistor.

公开(公告)号：US4099108A

公开(公告)日：1978-07-04

申请号：US716205

申请日：1976-08-20

Applicant: Tadashi Okawa ,  Yasuo Matsuda ,  Hiroshi Hayashida ,  Takeo Maeda

Inventor： Tadashi Okawa ,  Yasuo Matsuda ,  Hiroshi Hayashida ,  Takeo Maeda

IPC: H02P27/06 ,  H02P5/40

CPC classification number: H02P27/06 ,  H02P2201/03 ,  H02P27/047

Abstract: An induction motor is operated by a power supply of variable voltage and variable frequency. The voltage and frequency of the variable-voltage variable-frequency power supply is changed by a control circuit to accelerate or decelerate the induction motor. For slowly controlling the speed of the induction motor, the ratio of the output voltage to the output frequency of the variable-voltage variable-frequency power supply is maintained substantially constant. The control circuit includes a voltage correcting means which, in response to a command for sudden acceleration or deceleration of the speed of the motor, corrects the output voltage of the power supply in accordance with the acceleration or deceleration rate and the prevailing magnitude of the output frequency of the variable-voltage variable-frequency power supply.

Abstract translation: 感应电动机由可变电压和可变频率的电源操作。 可变电压可变频率电源的电压和频率由控制电路改变，以加速或减速感应电动机。 为了缓慢地控制感应电动机的速度，可变电压可变频率电源的输出电压与输出频率的比例保持基本恒定。 控制电路包括电压校正装置，响应于马达速度的突然加速或减速的命令，根据加速或减速率和输出的主要幅度来校正电源的输出电压 可变电压可变频率电源的频率。

公开(公告)号：US5677229A

公开(公告)日：1997-10-14

申请号：US430300

申请日：1995-04-28

Applicant: Shigeru Morita ,  Fumitomo Matsuoka ,  Hisao Yoshimura ,  Takeo Maeda

Inventor： Shigeru Morita ,  Fumitomo Matsuoka ,  Hisao Yoshimura ,  Takeo Maeda

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76237 ,  Y10S438/978

Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface of the projecting portion in a sloped shape, which is from the top portion of the projecting portion to the main surface.

Abstract translation: 本发明的半导体器件的制造方法具有在半导体基板的主面上形成绝缘材料的工序。 形成从材料膜的表面延伸到基底的凹槽。 凹槽用第一绝缘膜掩埋。 通过使用第一绝缘膜作为蚀刻掩模，去除材料膜，从而可以获得从主表面突出到第一绝缘膜的突出部分。 第二绝缘膜以从突出部分的顶部到主表面的倾斜形状形成在突出部分的侧表面上。

公开(公告)号：US5583363A

公开(公告)日：1996-12-10

申请号：US860596

申请日：1992-03-30

Applicant: Hiroshi Momose ,  Takeo Maeda ,  Koji Makita

Inventor： Hiroshi Momose ,  Takeo Maeda ,  Koji Makita

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/732 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/0716

Abstract: A semiconductor device comprises a p-type semiconductor substrate, an n-type semiconductor well formed on the substrate and connected to a positive power supply, a p-type semiconductor source formed within the n-type semiconductor well, a p-type semiconductor layer formed within the n-type semiconductor well and having a lower impurity concentration than the p-type semiconductor source, a first gate electrode formed over a region between the p-type semiconductor source and the p-type semiconductor layer through an insulating film, an n-type semiconductor emitter formed over the p-type semiconductor layer within the n-type semiconductor well, a first conductive layer formed over the n-type semiconductor well to connect with said p-type semiconductor source.

Abstract translation: 半导体器件包括p型半导体衬底，形成在衬底上并连接到正电源的n型半导体阱，形成在n型半导体阱内的p型半导体源，p型半导体层 形成在n型半导体阱内并且具有比p型半导体源低的杂质浓度;通过绝缘膜在p型半导体源和p型半导体层之间的区域上形成的第一栅电极， 在n型半导体阱内的p型半导体层上形成的n型半导体发射体，形成在n型半导体阱上并与所述p型半导体源连接的第一导电层。