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公开(公告)号：US20190025866A1
公开(公告)日：2019-01-24
申请号：US15832071
申请日：2017-12-05
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Vijayalakshmi Devarajan , Timothy Paul Duryea , Shanmuganand Chellamuthu
IPC: G05F3/26 , H03K17/687 , B60T8/1761 , B60T8/172
Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.
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12.发明申请公开(公告)号：US20190020338A1
公开(公告)日：2019-01-17
申请号：US15647825
申请日：2017-07-12
Applicant: Texas Instruments Incorporated
Inventor： Shanmuganand Chellamuthu , Kemal Safak Demirci , Anand Gopalan
CPC classification number: H03K17/145 , G05F1/56
Abstract: A voltage regulator and a gate control circuit for an aid transistor coupled to assist a pass element for the voltage regulator during line transients having a given slope are disclosed. The gate control circuit includes a first circuit coupled to receive an output voltage of the voltage regulator on a first node and to provide a gate control voltage that mirrors the output voltage on a second node. A low pass filter is coupled to receive the gate control voltage and to provide a filtered gate control voltage to the gate of the aid transistor.
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Patent Agency Ranking
公开(公告)号：US20150248137A1
公开(公告)日：2015-09-03
申请号：US14194103
申请日：2014-02-28
Applicant: Texas Instruments Incorporated
Inventor： Seenu Gopalraju , Patrick Michael Teterud , Shanmuganand Chellamuthu
Abstract: In response to a first reference voltage, a regulator regulates an output voltage of a line, so that the output voltage is approximately equal to a target voltage. In response to the output voltage rising above a second reference voltage, pull down circuitry draws current from the line. In response to the output voltage falling below the second reference voltage by at least a predetermined amount, the pull down circuitry ceases to draw current from the line. The first and second reference voltages are based upon a same band gap reference as one another.
Abstract translation: 响应于第一参考电压，调节器调节线路的输出电压，使得输出电压近似等于目标电压。 响应于输出电压上升到高于第二参考电压，下拉电路从线路中吸取电流。 响应于输出电压低于第二参考电压至少预定量，下拉电路停止从线路中吸取电流。 第一和第二参考电压基于彼此相同的带隙基准。
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公开(公告)号：US12072373B2
公开(公告)日：2024-08-27
申请号：US18117516
申请日：2023-03-06
Applicant: Texas Instruments Incorporated
Inventor： Kemal Safak Demirci , Shanmuganand Chellamuthu , Qunying Li
CPC classification number: G01R31/2853 , H03F3/45475 , H03K5/24 , H03K19/20
Abstract: A circuit includes a gain stage, first and second amplifiers, and a comparison circuit. The gain stage has an input and an output. The first amplifier has an input and an output. The input of the first amplifier is coupled to the input of the gain stage. The second amplifier has an input and an output. The input of the second amplifier is coupled to the output of the gain stage. The comparison circuit is coupled to the outputs of the first and second amplifiers. The comparison circuit is configured to compare signals on the outputs of the first and second amplifiers and to generate a fault flag signal responsive to the output signal from the first amplifier being different than the output signal from the second amplifier.
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公开(公告)号：US10382030B2
公开(公告)日：2019-08-13
申请号：US15647825
申请日：2017-07-12
Applicant: Texas Instruments Incorporated
Inventor： Shanmuganand Chellamuthu , Kemal Safak Demirci , Anand Gopalan
Abstract: A voltage regulator and a gate control circuit for an aid transistor coupled to assist a pass element for the voltage regulator during line transients having a given slope are disclosed. The gate control circuit includes a first circuit coupled to receive an output voltage of the voltage regulator on a first node and to provide a gate control voltage that mirrors the output voltage on a second node. A low pass filter is coupled to receive the gate control voltage and to provide a filtered gate control voltage to the gate of the aid transistor.
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公开(公告)号：US20180073895A1
公开(公告)日：2018-03-15
申请号：US15263114
申请日：2016-09-12
Applicant: Texas Instruments Incorporated
Abstract: An angular resolver system includes, for example, an imbalance detector for detecting degraded resolver output signals. The imbalance detector includes a first and second power averaging circuits and a comparator circuit. The first power averaging circuit includes a first integrator for generating over a first time window a first average power signal in response to resolver sensor output signals. The second power averaging circuit includes a second integrator for generating over a second time window a second average power signal in response to the resolver sensor output signals, where the first time window is longer than the second time window. The comparator circuit compares the first average power signal and the second average power signal and generates a fault signal when the first average power signal and the second average power signal differ by a selected voltage threshold.
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公开(公告)号：US20180052013A1
公开(公告)日：2018-02-22
申请号：US15276348
申请日：2016-09-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shanmuganand Chellamuthu , Viktor Tasevski , Ted F. Lekan , Fei Xu
IPC: G01D5/243
CPC classification number: G01D5/243 , G01D5/2073
Abstract: Methods, apparatus, systems and articles of manufacture to increase resolver-to-digital converter accuracy are disclosed. Example methods and apparatus compare a first induced signal and a first threshold signal to determine a first zero-cross signal, compare a second induced signal with the first threshold signal to determine a second zero-cross signal, compare an inducing signal with the first threshold signal to determine a third zero-cross signal, compare the first induced signal and a second threshold signal to determine a first zero-cross confirmation signal, the first zero-cross confirmation signal to indicate when to use the first zero-cross signal to determine a phase difference between the inducing signal and at least one of the first induced signal or the second induced signal, and compare the second induced sinusoidal signal and the second threshold signal to determine a second zero-cross confirmation signal, the second zero-cross confirmation signal to indicate when to use the second zero-cross signal to determine the phase difference.
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