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公开(公告)号：US09411353B2
公开(公告)日：2016-08-09
申请号：US14194103
申请日：2014-02-28
Applicant: Texas Instruments Incorporated
Inventor： Seenu Gopalraju , Patrick Michael Teterud , Shanmuganand Chellamuthu
Abstract: In response to a first reference voltage, a regulator regulates an output voltage of a line, so that the output voltage is approximately equal to a target voltage. In response to the output voltage rising above a second reference voltage, pull down circuitry draws current from the line. In response to the output voltage falling below the second reference voltage by at least a predetermined amount, the pull down circuitry ceases to draw current from the line. The first and second reference voltages are based upon a same band gap reference as one another.
Abstract translation: 响应于第一参考电压，调节器调节线路的输出电压，使得输出电压近似等于目标电压。 响应于输出电压上升到高于第二参考电压，下拉电路从线路中吸取电流。 响应于输出电压低于第二参考电压至少预定量，下拉电路停止从线路中吸取电流。 第一和第二参考电压基于彼此相同的带隙基准。
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公开(公告)号：US12088289B2
公开(公告)日：2024-09-10
申请号：US17350727
申请日：2021-06-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shanmuganand Chellamuthu , Qunying Li , Vikram Joseph Mani
IPC: H03K17/95 , H03B5/04 , H03B5/12 , H03K17/732
CPC classification number: H03K17/9542 , H03B5/04 , H03B5/1209 , H03K17/732
Abstract: A system includes a sensor integrated circuit (IC), including a driver adapted to be coupled to an oscillator, the driver including first and second transistors. The sensor IC includes an amplitude control amplifier coupled to the first transistor. The sensor IC also includes a common mode control amplifier coupled to the second transistor. The sensor IC includes a handover control circuit coupled to the amplitude control amplifier and configured to hand off an operation from the sensor IC to a different sensor IC, the handover control circuit including a resistor network coupled to a switch network.
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公开(公告)号：US11598802B2
公开(公告)日：2023-03-07
申请号：US17168528
申请日：2021-02-05
Applicant: Texas Instruments Incorporated
Inventor： Kemal Safak Demirci , Shanmuganand Chellamuthu , Qunying Li
Abstract: A circuit includes a gain stage, first and second amplifiers, and a comparison circuit. The gain stage has an input and an output. The first amplifier has an input and an output. The input of the first amplifier is coupled to the input of the gain stage. The second amplifier has an input and an output. The input of the second amplifier is coupled to the output of the gain stage. The comparison circuit is coupled to the outputs of the first and second amplifiers. The comparison circuit is configured to compare signals on the outputs of the first and second amplifiers and to generate a fault flag signal responsive to the output signal from the first amplifier being different than the output signal from the second amplifier.
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公开(公告)号：US09515655B2
公开(公告)日：2016-12-06
申请号：US14671436
申请日：2015-03-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shanmuganand Chellamuthu , Kemal Safak Demirci
IPC: H03K19/003
CPC classification number: H03K19/00315 , H03K19/00369 , Y10T307/675 , Y10T307/724
Abstract: A circuit includes an input pin connected to an integrated circuit (IC) that receives an input voltage that is provided to a first voltage circuit within the IC. A pass device having a control input responds to a first control signal state and a second control signal state. The first control signal state turns the pass device off such that the input voltage is switched off to block the passing of the input voltage to a second voltage circuit within the IC. The second control signal state turns the pass device on such that the input voltage is switched through the pass device to the second voltage circuit in a voltage range that is compatible with an input operating voltage range of the second voltage circuit.
Abstract translation: 电路包括连接到集成电路（IC）的输入引脚，该集成电路接收提供给IC内的第一电压电路的输入电压。 具有控制输入的通过装置响应于第一控制信号状态和第二控制信号状态。 第一控制信号状态使通过装置关闭，使得输入电压被关闭以阻止输入电压通过IC内的第二电压电路。 第二控制信号状态使得通过装置使得输入电压在与第二电压电路的输入工作电压范围兼容的电压范围内通过通过装置切换到第二电压电路。
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公开(公告)号：US10884037B2
公开(公告)日：2021-01-05
申请号：US15263114
申请日：2016-09-12
Applicant: Texas Instruments Incorporated
Abstract: An angular resolver system includes, for example, an imbalance detector for detecting degraded resolver output signals. The imbalance detector includes a first and second power averaging circuits and a comparator circuit. The first power averaging circuit includes a first integrator for generating over a first time window a first average power signal in response to resolver sensor output signals. The second power averaging circuit includes a second integrator for generating over a second time window a second average power signal in response to the resolver sensor output signals, where the first time window is longer than the second time window. The comparator circuit compares the first average power signal and the second average power signal and generates a fault signal when the first average power signal and the second average power signal differ by a selected voltage threshold.
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Patent Agency Ranking
公开(公告)号：US10784873B1
公开(公告)日：2020-09-22
申请号：US16391865
申请日：2019-04-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Qunying Li , Shanmuganand Chellamuthu , Kemal Safak Demirci
Abstract: A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.
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公开(公告)号：US10520971B2
公开(公告)日：2019-12-31
申请号：US15832071
申请日：2017-12-05
Applicant: Texas Instruments Incorporated
Inventor： Sri Navaneethakrishnan Easwaran , Vijayalakshmi Devarajan , Timothy Paul Duryea , Shanmuganand Chellamuthu
IPC: G05F3/26 , B60T8/172 , B60T8/1761 , H03K17/687
Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.
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公开(公告)号：US11611323B2
公开(公告)日：2023-03-21
申请号：US16591288
申请日：2019-10-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Qunying Li , Shanmuganand Chellamuthu
Abstract: An automatic gain control circuit includes a linear-to-log conversion circuit, a current amplifier circuit, and an amplitude sense circuit. The current amplifier circuit includes a current input terminal coupled to an output terminal of the linear-to-log conversion circuit. The amplitude sense circuit includes an input terminal coupled to an output terminal of the current amplifier circuit, and an output terminal coupled to a gain control input terminal of the current amplifier circuit.
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公开(公告)号：US10985763B2
公开(公告)日：2021-04-20
申请号：US16991072
申请日：2020-08-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Qunying Li , Shanmuganand Chellamuthu , Kemal Safak Demirci
Abstract: A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.
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公开(公告)号：US10408643B2
公开(公告)日：2019-09-10
申请号：US15276348
申请日：2016-09-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shanmuganand Chellamuthu , Viktor Tasevski , Ted F. Lekan , Fei Xu
Abstract: Methods, apparatus, systems and articles of manufacture to increase resolver-to-digital converter accuracy are disclosed. Example methods and apparatus compare a first induced signal and a first threshold signal to determine a first zero-cross signal, compare a second induced signal with the first threshold signal to determine a second zero-cross signal, compare an inducing signal with the first threshold signal to determine a third zero-cross signal, compare the first induced signal and a second threshold signal to determine a first zero-cross confirmation signal, the first zero-cross confirmation signal to indicate when to use the first zero-cross signal to determine a phase difference between the inducing signal and at least one of the first induced signal or the second induced signal, and compare the second induced sinusoidal signal and the second threshold signal to determine a second zero-cross confirmation signal, the second zero-cross confirmation signal to indicate when to use the second zero-cross signal to determine the phase difference.
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