公开(公告)号：US06965945B2

公开(公告)日：2005-11-15

申请号：US10083132

申请日：2002-02-27

申请人： Jonathan Lin ,  David Billings

发明人： Jonathan Lin ,  David Billings

IPC分类号： H04L12/56 ,  G06F15/173

CPC分类号： H04L45/742 ,  H04L49/3018 ,  H04L49/351 ,  H04L49/354 ,  Y10S707/99933

摘要： A network device including at least one network port, a clock, address resolution (ARL) tables, and address resolution logic. The at least one network port is configured to send and receive a data packet. The clock is for generating a timing signal. The ARL tables are configured to store and maintain data related to port addresses of the network device. The address resolution logic is coupled to the ARL tables and configured to perform a search and an update to data into the ARL tables based on the data packet, to calculate a current range of the search, to determine an intended result of the update, and to block the update when the intended result will move data out of the current range of the search, the search and the update being performed concurrently during alternating slots of the timing signal.

摘要翻译： 包括至少一个网络端口，时钟，地址解析（ARL）表和地址解析逻辑的网络设备。 所述至少一个网络端口被配置为发送和接收数据分组。 时钟用于产生定时信号。 ARL表被配置为存储和维护与网络设备的端口地址相关的数据。 地址解析逻辑耦合到ARL表并且被配置为基于数据分组来执行对ARL表的数据的搜索和更新，以计算搜索的当前范围，以确定更新的预期结果，以及 当预期结果将数据移出搜索的当前范围时，阻止更新，搜索和更新在定时信号的交替时隙期间同时执行。

公开(公告)号：US20050076035A1

公开(公告)日：2005-04-07

申请号：US10965728

申请日：2004-10-18

申请人： Jonathan Lin ,  David Billings ,  Mike Jorda

发明人： Jonathan Lin ,  David Billings ,  Mike Jorda

IPC分类号： G06F17/30

CPC分类号： G06F17/30946 ,  Y10S707/99933 ,  Y10S707/99938

摘要： A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory banks. The queue management unit is configured to receive a plurality of search requests and to prioritize the search requests. The memory management unit is coupled to the queue management unit and the memory, and is configured to initiate a plurality of binary searches based on the plurality of search requests. Each binary search is executed simultaneously in different banks of the plurality of memory banks. The search switching unit is coupled to the memory and the memory management unit, and is configured to switch each binary search from one memory bank of to another memory bank after a predetermined number of search steps are performed by each binary search.

摘要翻译： 一种网络设备，包括存储器，队列管理单元，存储器管理单元和搜索切换单元。 存储器包括多个存储体。 队列管理单元被配置为接收多个搜索请求并且优先处理搜索请求。 存储器管理单元耦合到队列管理单元和存储器，并且被配置为基于多个搜索请求发起多个二进制搜索。 在多个存储体的不同的存储体中同时执行每个二进制搜索。 搜索切换单元耦合到存储器和存储器管理单元，并且被配置为在通过每个二进制搜索执行预定数量的搜索步骤之后将每个二进制搜索从一个存储体切换到另一个存储体。

公开(公告)号：US5615150A

公开(公告)日：1997-03-25

申请号：US551974

申请日：1995-11-02

申请人： Jonathan Lin ,  Radu Barsan

发明人： Jonathan Lin ,  Radu Barsan

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C11/34

CPC分类号： G11C16/045 ,  G11C16/0441 ,  H01L27/115 ,  G11C2216/10

摘要： An improved control gate-addressed CMOS memory cell is provided which allows for programming and erasing by tunneling through the gate oxides of the PMOS and NMOS transistors. The CMOS memory cell (400) includes a PMOS transistor (402), an NMOS transistor (403), and an NMOS pass transistor (405). A capacitor (430) has a first terminal coupled to a common floating gate (416) of the PMOS and NMOS transistors and has a second terminal coupled to a control gate node.

摘要翻译： 提供了一种改进的控制栅极寻址CMOS存储单元，其允许通过穿过PMOS和NMOS晶体管的栅极氧化物的隧道编程和擦除。 CMOS存储单元（400）包括PMOS晶体管（402），NMOS晶体管（403）和NMOS传输晶体管（405）。 电容器（430）具有耦合到PMOS和NMOS晶体管的公共浮动栅极（416）的第一端子，并且具有耦合到控制栅极节点的第二端子。

公开(公告)号：US5604370A

公开(公告)日：1997-02-18

申请号：US501230

申请日：1995-07-11

申请人： Sunil Mehta ,  Jonathan Lin

发明人： Sunil Mehta ,  Jonathan Lin

IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/0638 ,  H01L21/762

摘要： The concentration of impurities at the surface of the semiconductor device adjacent and under the bird's beak of a field oxide region is reduced by employing sidewall spacers prior to field implantation. The resulting semiconductor device exhibits reduced sidewall junction capacitance and leakage, an increased junction breakdown voltage and a reduced narrow channel effect.

摘要翻译： 通过在野外植入之前采用侧壁间隔，在场氧化物区域的鸟喙附近和下方的半导体器件的表面处的杂质浓度降低。 所得到的半导体器件表现出降低的侧壁结电容和泄漏，增加的结击穿电压和减小的窄通道效应。

公开(公告)号：US5594687A

公开(公告)日：1997-01-14

申请号：US447991

申请日：1995-05-23

申请人： Jonathan Lin ,  Radu Barsan ,  Bradley A. Sharpe-Geisler

发明人： Jonathan Lin ,  Radu Barsan ,  Bradley A. Sharpe-Geisler

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： G11C16/045 ,  G11C16/0441 ,  H01L27/115 ,  G11C2216/10

摘要： Circuitry added to CMOS memory cell configured to enable tunneling through its PMOS and NMOS transistors, the circuitry preventing leakage current during programming. The circuitry includes a separate NMOS pass gate for connecting the source of the NMOS transistor of the CMOS cell to Vss. The gate of the NMOS pass gate is controlled to turn off the NMOS transistor during programming through the PMOS transistor to prevent current loss on the Vss line. The NMOS pass gate further provides a means for enabling or disabling the NMOS transistor making the CMOS cell useful as an array cell for a PAL device.

摘要翻译： 电路添加到CMOS存储器单元中，配置为能够通过其PMOS和NMOS晶体管进行隧穿，该电路可防止编程期间的漏电流。 该电路包括用于将CMOS单元的NMOS晶体管的源极连接到Vss的单独的NMOS通孔。 在通过PMOS晶体管的编程期间，NMOS栅极的栅极被控制为关闭NMOS晶体管，以防止Vss线上的电流损耗。 NMOS栅极进一步提供用于启用或禁用NMOS晶体管的装置，其使得CMOS单元可用作PAL器件的阵列单元。

公开(公告)号：US5587945A

公开(公告)日：1996-12-24

申请号：US554092

申请日：1995-11-06

申请人： Jonathan Lin ,  Jack Z. Peng ,  Radu Barsan ,  Sunil Mehta

发明人： Jonathan Lin ,  Jack Z. Peng ,  Radu Barsan ,  Sunil Mehta

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C16/02

CPC分类号： G11C16/045 ,  G11C16/0441 ,  H01L27/115 ,  G11C2216/10

摘要： A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.

摘要翻译： CMOS存储单元包括具有公共浮动栅极的PMOS和NMOS晶体管。 CMOS存储单元包括将第一控制电压连接到公共浮置栅极的第一电容器和从公共浮置栅极连接到NMOS晶体管的源极的第二隧穿电容器。 隧道电容器包括用于在编程或擦除期间对浮动栅极充电或放电的隧道氧化物区域。 CMOS单元还包括具有将NMOS晶体管的源极连接到第二控制电压的源极到漏极路径的传输晶体管。

公开(公告)号：US07134010B2

公开(公告)日：2006-11-07

申请号：US11149182

申请日：2005-06-10

申请人： Jonathan Lin ,  Yong Jiang

发明人： Jonathan Lin ,  Yong Jiang

IPC分类号： G03F7/38

CPC分类号： G06F13/385 ,  H03L7/0812 ,  H04J3/0697 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354 ,  H04L49/40

摘要： A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port. The external clock signal is input to the programmable delay locked loop, which outputs an output clock signal having a frequency equal to the frequency of the external clock signal, in synchronization with the data being output.

公开(公告)号：US07024576B2

公开(公告)日：2006-04-04

申请号：US11180628

申请日：2005-07-14

申请人： Jonathan Lin ,  Yong Jiang

发明人： Jonathan Lin ,  Yong Jiang

IPC分类号： G04F8/00

CPC分类号： H03L7/00 ,  H04J3/0697 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/0337 ,  H04L7/0338 ,  H04L25/14

摘要： A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

公开(公告)号：US06813620B2

公开(公告)日：2004-11-02

申请号：US10083591

申请日：2002-02-27

申请人： Jonathan Lin ,  David Billings ,  Mike Jorda

发明人： Jonathan Lin ,  David Billings ,  Mike Jorda

IPC分类号： G06F1730

CPC分类号： G06F17/30946 ,  Y10S707/99933 ,  Y10S707/99938

摘要： A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory banks. The queue management unit is configured to receive a plurality of search requests and to prioritize the search requests. The memory management unit is coupled to the queue management unit and the memory, and is configured to initiate a plurality of binary searches based on the plurality of search requests. Each binary search is executed simultaneously in different banks of the plurality of memory banks. The search switching unit is coupled to the memory and the memory management unit, and is configured to switch each binary search from one memory bank of to another memory bank after a predetermined number of search steps are performed by each binary search.

摘要翻译： 一种网络设备，包括存储器，队列管理单元，存储器管理单元和搜索切换单元。 存储器包括多个存储体。 队列管理单元被配置为接收多个搜索请求并且优先处理搜索请求。 存储器管理单元耦合到队列管理单元和存储器，并且被配置为基于多个搜索请求发起多个二进制搜索。 在多个存储体的不同的存储体中同时执行每个二进制搜索。 搜索切换单元耦合到存储器和存储器管理单元，并且被配置为在通过每个二进制搜索执行预定数量的搜索步骤之后将每个二进制搜索从一个存储体切换到另一个存储体。

公开(公告)号：US5908308A

公开(公告)日：1999-06-01

申请号：US980883

申请日：1997-11-26

申请人： Radu Barsan ,  Jonathan Lin ,  Sunil Mehta

发明人： Radu Barsan ,  Jonathan Lin ,  Sunil Mehta

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H11L21/8238 ,  H01L21/31 ,  H01L21/336 ,  H01L21/469 ,  H01L21/76

CPC分类号： H01L21/02129 ,  H01L21/31625 ,  H01L21/76202 ,  H01L21/76834 ,  H01L21/823475

摘要： Controlling the thickness of borophosphorous tetraethyl orthosilicate (BPTEOS) used as all or part of the first inter-layer dielectric (ILD0) in manufacturing a semiconductor device containing an array of transistors to control the field leakage between transistors. Reducing field leakage enables the thickness of field oxide, typically used to reduce field leakage, to be reduced to increase device density in the transistor array.

摘要翻译： 控制在制造包含晶体管阵列以控制晶体管之间的场漏电的半导体器件中用作全部或部分第一层间电介质（ILD0）的硼磷酸四乙基原硅酸盐（BPTEOS）的厚度。 减小场漏电流使得通常用于减少场漏电的场氧化物的厚度减小以增加晶体管阵列中的器件密度。