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公开(公告)号：US07310755B2
公开(公告)日：2007-12-18
申请号：US10779817
申请日：2004-02-18
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit having a plurality of processing stages includes a low power mode controller operable to control the integrated circuit to switch between an operational mode and a standby mode. At least one of the processing stages has a non-delayed latch to capture a non-delayed value of an output signal from that processing stage and a delayed latch operable during the operational mode to capture a delayed value of the same signal. A difference between these two captured signals is indicative of the processing operation not being completed at the time the non-delayed signal was captured. The delayed latch is operable during the standby mode to retain the signal it captured whilst the non-delayed latch is powered down and loses its value. The delayed latch is formed to have a lower power consumption than the non-delayed latch.
摘要翻译： 具有多个处理级的集成电路包括可操作以控制集成电路在操作模式和待机模式之间切换的低功率模式控制器。 处理级中的至少一个具有非延迟锁存器，以捕获来自该处理级的输出信号的非延迟值，以及在操作模式期间可操作以捕获相同信号的延迟值的延迟锁存器。 这两个捕获信号之间的差异表示在捕获非延迟信号时处理操作未完成。 延迟锁存器在待机模式期间可操作以保持其捕获的信号，同时非延迟锁存器断电并失去其值。 延迟锁存器形成为具有比非延迟锁存器更低的功耗。
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公开(公告)号：US20110107166A1
公开(公告)日：2011-05-05
申请号：US12926084
申请日：2010-10-25
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/00 , G06F11/0706 , G06F11/0736 , G06F11/0754 , G06F11/0757 , G06F11/079 , G06F11/1402 , G06F11/1604
摘要： An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.
摘要翻译： 集成电路包括具有错误检测和误差校正电路的一个或多个部分，并且其操作参数给出有限的非零误码率以及形成和操作以提供零错误率的一个或多个部分。
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公开(公告)号：US20110093737A1
公开(公告)日：2011-04-21
申请号：US12923911
申请日：2010-10-13
IPC分类号： G06F11/07
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
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14.发明授权公开(公告)号：US07650551B2
公开(公告)日：2010-01-19
申请号：US11889759
申请日：2007-08-16
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑2，非延迟锁存器4，延迟锁存器8和比较器6.非延迟锁存器4以非延迟捕获来自处理逻辑2的输出 捕捉时间。 在稍后的延迟捕获时间，延迟锁存器8也从处理逻辑2中捕获一个值。比较器6比较这些值，如果它们不相等，则表示非延迟值被捕获得太早，应该由 延迟值。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。
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15.发明授权Performance level selection in a data processing system by combining a plurality of performance requests 有权通过组合多个性能请求在数据处理系统中进行性能级别选择公开(公告)号：US07512820B2
公开(公告)日：2009-03-31
申请号：US11520007
申请日：2006-09-13
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.
摘要翻译： 通过使用多个性能请求计算算法来计算多个性能请求来执行性能级别选择，组合那些不同的性能请求以形成全局性能请求，然后根据全局性能级别请求选择性能级别。 可以将性能请求计算算法排列在层次结构中，其性能请求以从层次结构中的最低主导位置开始的序列进行评估，并且移动到层次结构中最主要的位置。 命令可以伴随每个性能级别请求来指定如何与其他性能级别请求组合。
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16.发明授权Performance level selection in a data processing system using a plurality of performance request calculating algorithms 有权使用多个性能请求计算算法的数据处理系统中的性能级别选择公开(公告)号：US07131015B2
公开(公告)日：2006-10-31
申请号：US10687972
申请日：2003-10-20
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.
摘要翻译： 通过使用多个性能请求计算算法来计算多个性能请求来执行性能级别选择，组合那些不同的性能请求以形成全局性能请求，然后根据全局性能级别请求选择性能级别。 可以将性能请求计算算法排列成层次结构，其性能请求以从层次结构中的最低主导位置开始的序列进行评估，并且移动到层次结构中最主要的位置。 命令可以伴随每个性能级别请求来指定如何与其他性能级别请求组合。
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17.发明授权Performance counter for adding variable work increment value that is dependent upon clock frequency 有权用于添加依赖于时钟频率的可变工作增量值的性能计数器公开(公告)号：US07321942B2
公开(公告)日：2008-01-22
申请号：US10687924
申请日：2003-10-20
IPC分类号： G06F3/00
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance counter accumulates a value by periodically adding a variable increment value representing the amount of work performed. The increment value can be varied in dependence upon the processor clock frequency and may be adjusted under hardware and/or software control.
摘要翻译： 性能计数器通过周期性地添加表示所执行的工作量的可变增量值累加值。 增量值可以根据处理器时钟频率而变化，并且可以在硬件和/或软件控制下进行调整。
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公开(公告)号：US07194385B2
公开(公告)日：2007-03-20
申请号：US10687928
申请日：2003-10-20
IPC分类号： G06F11/30
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A target processor performance level is calculated from a utilisation history of a processor in performance of a plurality of processing tasks. The method comprises calculating a task work value indicating processor utilisation in performing a given processing task within a predetermined task time-interval and calculating a target processor performance level in dependence upon the task work value.
摘要翻译： 在执行多个处理任务时，从处理器的利用历史计算目标处理器性能级别。 该方法包括：计算在预定任务时间间隔内执行给定处理任务的处理器利用率的任务工作值，并根据任务工作值计算目标处理器性能水平。
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公开(公告)号：US08505002B2
公开(公告)日：2013-08-06
申请号：US11905160
申请日：2007-09-27
申请人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
发明人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
IPC分类号： G06F9/45
CPC分类号： G06F9/30054 , G06F9/30032 , G06F9/30036 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3885 , G06F9/3887 , G06F9/45516
摘要： A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.
摘要翻译： 提供了一种数据处理系统，其具有处理器和分析电路，用于识别与第一SIMD指令集相关联的SIMD指令，并通过功能等效的标量表示代替它并标记该功能等效的标量表示。 标记的功能等效标量表示在执行程序时使用转换电路进行动态转换，以生成对应于与所识别的SIMD指令相对应的第一SIMD架构不同的指令集架构的一个或多个相应的转换指令。
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公开(公告)号：US20090049331A1
公开(公告)日：2009-02-19
申请号：US11887106
申请日：2005-10-03
IPC分类号： G06F11/20
CPC分类号： G06F11/261 , G06F17/5045 , Y02T10/82
摘要： A method of selecting where error detection circuits should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify error propagation characteristics. Thus, registers at which propagated errors are highly likely to manifest themselves or which protect key architectural state, or which protect state not otherwise protected can be identified and so an efficient deployment of error detection mechanisms achieved. Within an integrated circuit output signals from inactive circuit elements may be subject to isolation gating in dependence upon a detected current state of the integrated circuit. Thus, inactive circuit elements in which soft errors occur have inappropriate output signals gated from reaching the rest of the integrated circuit and thus reducing erroneous operation.
摘要翻译： 选择错误检测电路应放置在集成电路中的方法，使用注入到测试设计中的错误的参考和测试设计的仿真，然后扇出对这些注入错误进行的分析，以识别误差传播特性。 因此，可以识别传播错误很可能表现自身或者保护关键体系结构状态或哪个保护状态没有被其他方式保护的寄存器，从而实现错误检测机制的有效部署。 在集成电路内，根据检测到的集成电路的当前状态，来自非活动电路元件的输出信号可能经受隔离门控。 因此，出现软错误的无效电路元件具有不适当的输出信号，从而不能到达集成电路的其余部分，从而减少错误的操作。
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