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11.发明授权Optimizing critical dimension uniformity utilizing a resist bake plate simulator 有权使用抗蚀剂烘烤板模拟器优化临界尺寸均匀性公开(公告)号：US07334202B1
公开(公告)日：2008-02-19
申请号：US11145327
申请日：2005-06-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G03F7/38 , G06F2217/80
摘要： A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.
摘要翻译： 提供了一种用于优化半导体制造工艺中的关键尺寸均匀性的系统。 该系统包括用于对物理烘烤板进行建模的烤盘模拟器。 有限元分析引擎使用来自烘烤板模拟器的信息来计算缺失的信息。 光刻模拟器使用来自烘烤板模拟器和有限元分析引擎的信息来预测光刻工艺的结果。 该系统可以以预测能力使用或作为过程控制系统的一部分使用。
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12.发明申请SYSTEM AND METHOD FOR IMPRINT LITHOGRAPHY TO FACILITATE DUAL DAMASCENE INTEGRATION WITH TWO IMPRINT ACTS 有权系统和方法，用于绘制两幅印刷动画的双重增强整合公开(公告)号：US20070283883A1
公开(公告)日：2007-12-13
申请号：US11741991
申请日：2007-04-30
IPC分类号： C23C10/00
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译： 提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。 该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。 该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。 通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。 沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。 当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。 一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。
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公开(公告)号：US07295288B1
公开(公告)日：2007-11-13
申请号：US11000869
申请日：2004-12-01
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： Systems and methodologies are provided that account for surface variations of a wafer by adjusting grating features of an imprint lithography mask. Such adjustment employs piezoelectric elements as part of the mask, which can change dimensions (e.g., a height change) and/or move when subjected to an electric voltage. Accordingly, by regulating the amount of electric voltage applied to the piezoelectric elements a controlled expansion for such elements can be obtained, to accommodate for topography variations of the wafer surface.
摘要翻译： 提供了通过调节压印光刻掩模的光栅特征来考虑晶片的表面变化的系统和方法。 这种调节使用压电元件作为掩模的一部分，其可以在经受电压时改变尺寸（例如，高度变化）和/或移动。 因此，通过调节施加到压电元件的电压量，可以获得这些元件的受控膨胀，以适应晶片表面的形貌变化。
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14.发明授权System and method for imprint lithography to facilitate dual damascene integration with two imprint acts 有权用于压印光刻的系统和方法，以促进双重镶嵌与两个印记动作的整合公开(公告)号：US07235474B1
公开(公告)日：2007-06-26
申请号：US10838612
申请日：2004-05-04
IPC分类号： H01L21/44
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译： 提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。 该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。 该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。 通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。 沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。 当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。 一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。
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公开(公告)号：US20070082277A1
公开(公告)日：2007-04-12
申请号：US11245824
申请日：2005-10-07
申请人： Itty Matthew , Bhanwar Singh
发明人： Itty Matthew , Bhanwar Singh
CPC分类号： G03F1/36
摘要： The subject invention provides a system and method for improving the process margin of a lithographic imaging system. The process margin improvement is achieved through the novel placement of discrete assist features and/or the use of forbidden pitches and specific pitch orientations. Novel geometries are utilized, which take advantage of line-end pull back and/or a lack of resolution of pitches perpendicular to an axis of a dipole illumination source. The strategic placement of a series of discrete scatterbar segments on a mask near positions of critical features, such as, for example, contacts, mitigates resist residue that can result from the use of a contiguous scatterbar.
摘要翻译： 本发明提供了一种用于改善光刻成像系统的工艺余量的系统和方法。 通过新颖的离散辅助特征的放置和/或使用禁止间距和特定的俯仰方向来实现工艺余量的改善。 利用新的几何形状，其利用垂直于偶极照明源的轴线的线端拉回和/或缺少分支的分辨率。 在临界特征（例如接触）位置附近的掩模上的一系列离散散射片段的战略布置减轻了抵抗可能由于使用连续散射线而产生的残留物。
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公开(公告)号：US07158896B1
公开(公告)日：2007-01-02
申请号：US10978604
申请日：2004-11-01
申请人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
发明人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
IPC分类号： G06F19/00
CPC分类号： G03F7/70916 , G03F7/2041 , G03F7/70341
摘要： Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.
摘要翻译： 公开了用于测量和/或控制溶解在浸入式光刻中使用的浸渍介质中的杂质量的系统和/或方法。 杂质可以是来自涂覆在基材表面上的光致抗蚀剂层的光致抗蚀剂。 已知的光栅结构被构建在衬底上。 实时浸没介质监测部件通过利用从已知光栅结构散射的光来便于测量和/或控制溶解在浸没介质中的杂质的量。
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17.发明授权公开(公告)号：US07079975B1
公开(公告)日：2006-07-18
申请号：US09845231
申请日：2001-04-30
CPC分类号： G01B11/0683 , G01B11/0625 , G01B17/025 , G01N21/47 , G01N21/8422 , G01N21/88 , G01N21/94
摘要： A system for monitoring and controlling the deposition of thin films employed in semiconductor fabrication is provided. The system includes one or more acoustic and/or ultrasonic wave sources, each source directing waves onto one or more thin films deposited on a wafer. Waves reflected from the thin film is collected by a monitoring system, which processes the collected waves. Waves passing through the thin film may similarly be collected by the monitoring system, which processes the collected waves. The collected waves are indicative of the presence of impurities and/or defects in the deposited thin film. The monitoring system analyzes and provides the collected wave data to a processor, which determines whether adjustments to thin film deposition parameters are needed. The system also includes a plurality of thin film deposition devices associated with depositing thin films on the wafer. The processor selectively controls thin film deposition parameters and devices to facilitate regulating deposition.
摘要翻译： 提供了用于监测和控制用于半导体制造中的薄膜沉积的系统。 该系统包括一个或多个声波和/或超声波波束，每个源将波束引导到沉积在晶片上的一个或多个薄膜上。 从薄膜反射的波浪由监测系统收集，监测系统处理收集的波。 通过薄膜的波浪可以类似地由监测系统收集，监测系统处理所收集的波。 收集的波表示沉积的薄膜中存在杂质和/或缺陷。 监测系统分析并将收集的波数据提供给处理器，其确定是否需要对薄膜沉积参数进行调整。 该系统还包括与在晶片上沉积薄膜相关联的多个薄膜沉积装置。 处理器选择性地控制薄膜沉积参数和装置以便于调节沉积。
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公开(公告)号：US07078348B1
公开(公告)日：2006-07-18
申请号：US09893188
申请日：2001-06-27
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76811 , H01L21/76813
摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.
摘要翻译： 本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。
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公开(公告)号：US07052575B1
公开(公告)日：2006-05-30
申请号：US09845454
申请日：2001-04-30
IPC分类号： C23F1/00
CPC分类号： H01L21/67253 , H01J37/32935 , H01L21/67063 , H01L22/34
摘要： A system for regulating an etch process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the acceptability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor selectively controls the etching devices to regulate etching of the portions of the wafer.
摘要翻译： 提供了一种用于调节蚀刻工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。 所收集的光指示在晶片的相应部分处获得的尺寸。 测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可接受性。 该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。 处理器选择性地控制蚀刻装置来调节晶片的部分的蚀刻。
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20.发明授权System and method of pattern recognition and metrology structure for an X-initiative layout design 失效用于X主动布局设计的模式识别和计量结构的系统和方法公开(公告)号：US07001830B2
公开(公告)日：2006-02-21
申请号：US10653309
申请日：2003-09-02
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
CPC分类号： G03F7/70625 , G03F7/70633 , G03F9/7076 , Y10S438/975
摘要： The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.
摘要翻译： 本发明涉及用于提供用于检查晶片的最佳方法的检查方法和系统。 该方法和系统包括晶片到标线片对准，层间对准和晶片表面特征检查。 通过将对角线添加到现有的对准标记来减小交叉点大小和期望点可以驻留的对应区域来改善晶片到标线阵列对准。 通过向现有覆盖目标添加倾斜和/或非线性线段，以类似的方式改善了层间对齐。 此外，在多个所需的对角轴中提供晶片表面检查允许更精确的特征测量。
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