Semiconductor device and manufacturing method thereof
    11.
    发明申请
    Semiconductor device and manufacturing method thereof 审中-公开
    半导体装置及其制造方法

    公开(公告)号:US20060091474A1

    公开(公告)日:2006-05-04

    申请号:US11260188

    申请日:2005-10-28

    IPC分类号: H01L29/76

    CPC分类号: H01L21/823842

    摘要: The manufacturing process of a semiconductor device in which a n channel MIS transistor and a p channel MIS transistor each having a gate electrode made of a metal material formed on a gate insulator made of a high dielectric constant material are used to form a CMOS circuit is simplified. After simultaneously forming the gate electrodes of the n channel MIS transistor and the p channel MIS transistor by patterning a platinum film deposited on a gate insulator made of a hafnium oxide film, only the gate insulator on the side of the n channel MIS transistor is selectively reduced by using the catalytic reduction of the platinum film. By doing so, the work function of the gate electrode of the n channel MIS transistor is changed.

    摘要翻译: 使用其中使用由具有由高介电常数材料制成的栅极绝缘体上形成的由金属材料制成的栅电极的n沟道MIS晶体管和p沟道MIS晶体管形成CMOS电路的半导体器件的制造工艺来形成CMOS电路。 在通过对沉积在由氧化铪膜构成的栅极绝缘体上的铂膜进行图案化而同时形成n沟道MIS晶体管和p沟道MIS晶体管的栅极之后,仅选择性地在n沟道MIS晶体管侧的栅极绝缘体 通过使用铂膜的催化还原来减少。 通过这样做,改变n沟道MIS晶体管的栅电极的功函数。

    Semiconductor device and manufacturing method thereof
    12.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号:US07323381B2

    公开(公告)日:2008-01-29

    申请号:US11180657

    申请日:2005-07-14

    IPC分类号: H01L21/8238

    CPC分类号: H01L21/823842

    摘要: A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.

    摘要翻译: 提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪(HfO 2 O 2)膜组成。 此外,n沟道MIS晶体管的栅电极由Ni(镍)硅化物膜构成,p沟道MIS晶体管的栅电极由Pt(铂)膜构成。 在这种结构中,可以防止栅电极的费米能级钉扎。 因此,可以抑制n沟道MIS晶体管和p沟道MIS晶体管的阈值电压的增加。

    Semiconductor device and manufacturing method thereof
    13.
    发明申请
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号:US20060051915A1

    公开(公告)日:2006-03-09

    申请号:US11180657

    申请日:2005-07-14

    IPC分类号: H01L21/8238 H01L21/8234

    CPC分类号: H01L21/823842

    摘要: A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.

    摘要翻译: 提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪(HfO 2 O 2)膜组成。 此外,n沟道MIS晶体管的栅电极由Ni(镍)硅化物膜构成,p沟道MIS晶体管的栅电极由Pt(铂)膜构成。 在这种结构中,可以防止栅电极的费米能级钉扎。 因此,可以抑制n沟道MIS晶体管和p沟道MIS晶体管的阈值电压的增加。

    Semiconductor device and manufacturing method thereof
    14.
    发明申请
    Semiconductor device and manufacturing method thereof 审中-公开
    半导体装置及其制造方法

    公开(公告)号:US20050285206A1

    公开(公告)日:2005-12-29

    申请号:US11142796

    申请日:2005-06-02

    摘要: The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is comprised of metal silicide containing Ni, metal with a work function lower than that of Ni, and Si, and a gate electrode of a p channel MISFET is comprised of metal silicide containing Ni, metal with a work function higher than that of Ni, and Si. Since metal with a work function lower than that of Ni is contained in the gate electrode of the n channel MISFET and metal with a work function higher than that of Ni is contained in the gate electrode of the p channel MISFET, the threshold voltage can be reduced in both the n channel MISFET and the p channel MISFET. Also, the gate electrodes are formed by reacting a nondope silicon film with a metal film.

    摘要翻译: 提高了半导体器件的性能和可靠性。 在具有CMISFET的半导体器件中,n沟道MISFET的栅极由包含Ni的金属硅化物,功函数低于Ni的金属和Si构成,并且p沟道MISFET的栅电极由金属 含Ni的硅化物,功函数高于Ni的金属和Si。 由于在n沟道MISFET的栅电极中含有功函数低于Ni的金属,所以在p沟道MISFET的栅电极中含有功函数高于Ni的功能金属,所以阈值电压可以是 在n沟道MISFET和p沟道MISFET两者中减小。 此外,栅电极通过使非钝化硅膜与金属膜反应而形成。

    Semiconductor device and production method thereof
    15.
    发明授权
    Semiconductor device and production method thereof 失效
    半导体装置及其制造方法

    公开(公告)号:US06483167B1

    公开(公告)日:2002-11-19

    申请号:US09644716

    申请日:2000-08-23

    IPC分类号: H01L2900

    CPC分类号: H01L28/60 H01L28/55 H01L28/91

    摘要: In a semiconductor device and production method thereof, a technique is used to prevent film separation of the bottom electrode occurring during a heat treatment process which is carried out to make the bottom electrode closely packed and in the heat treatment process for producing dielectric crystallization. In the production method, a glue layer including an insulator is formed between SiO2 insulation layer and the inner wall of a concave hole. The SiO2 layer 14 is located on the Si board 11, and Si plug 12 and a barrier layer 13 are formed therein. A glue layer 16 is formed on the inner wall of the hole of the SiO2 insulation layer 15, and a bottom electrode 17 comprising Ru is formed on the barrier layer 13 and glue layer 16. Dielectric film 18 comprising BST and a top electrode 19 comprising Ru are laminated sequentially on the bottom electrode 17, to form a dielectric device with the bottom electrode 17.

    摘要翻译: 在半导体装置及其制造方法中,使用这样的技术来防止在进行底部电极紧密堆积的热处理过程中发生的底部电极的膜分离和用于产生电介质结晶的热处理工艺。 在制造方法中,在SiO2绝缘层和凹孔的内壁之间形成包含绝缘体的胶层。 SiO 2层14位于Si基板11上,形成Si塞12和阻挡层13。 在SiO 2绝缘层15的孔的内壁上形成胶层16,在阻挡层13和胶层16上形成包含Ru的底部电极17.包含BST的电介质膜18和顶部电极19包括 Ru依次层叠在底部电极17上,形成具有底部电极17的电介质器件。

    Semiconductor device having misfet gate electrodes with and without GE or impurity and manufacturing method thereof
    16.
    发明授权
    Semiconductor device having misfet gate electrodes with and without GE or impurity and manufacturing method thereof 有权
    具有和不具有GE或杂质的偏移栅电极的半导体器件及其制造方法

    公开(公告)号:US07202539B2

    公开(公告)日:2007-04-10

    申请号:US11132373

    申请日:2005-05-19

    IPC分类号: H01L29/76

    摘要: The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a gate electrode of a p channel MISFET is composed of a nickel-silicon-germanium film formed by reacting a nondope silicon germanium film with the Ni film. The work function of the gate electrode of the n channel MISFET is controlled by doping P, As, or Sb, and the work function of the gate electrode of the p channel MISFET is controlled by adjusting the Ge concentration.

    摘要翻译: 提高了半导体器件的性能和可靠性。 在具有CMISFET的半导体器件中,n沟道MISFET的栅电极由通过使掺杂有P,As或Sb的硅膜与Ni膜反应而形成的硅化镍膜,以及p沟道MISFET的栅电极 由通过非钝化硅锗膜与Ni膜反应形成的镍硅锗膜构成。 通过掺杂P,As或Sb来控制n沟道MISFET的栅电极的功函数,并且通过调整Ge浓度来控制p沟道MISFET的栅电极的功函数。

    Semiconductor device and manufacturing method of the same
    17.
    发明申请
    Semiconductor device and manufacturing method of the same 审中-公开
    半导体器件及其制造方法相同

    公开(公告)号:US20060278937A1

    公开(公告)日:2006-12-14

    申请号:US11448110

    申请日:2006-06-07

    IPC分类号: H01L29/76

    摘要: As shown in FIG. 2B, a gate electrode is formed on a gate insulating film on a semiconductor substrate. A high dielectric film with a dielectric constant higher than that of a silicon oxide film is used for the gate insulating film, and a platinum-rich silicide film is used for the gate electrode. The platinum-rich silicide film indicates a film with a ratio of silicon atoms to platinum atoms of less than 1 (PtSix: x

    摘要翻译: 如图所示。 如图2B所示,在半导体衬底上的栅极绝缘膜上形成栅电极。 对于栅极绝缘膜使用介电常数高于氧化硅膜的高电介质膜,并且将富铂的硅化物膜用于栅电极。 富含铂的硅化物膜表示硅原子与铂原子的比率小于1(PtSix:x <1)的膜。 作为导电杂质的硼被引入到由富铂的硅化物膜构成的栅电极中,并且硼在栅极绝缘膜和栅电极之间的界面处分离。

    Semiconductor device and manufacturing method thereof
    18.
    发明申请
    Semiconductor device and manufacturing method thereof 审中-公开
    半导体装置及其制造方法

    公开(公告)号:US20060071282A1

    公开(公告)日:2006-04-06

    申请号:US11242909

    申请日:2005-10-05

    IPC分类号: H01L29/94

    摘要: A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of a n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide film. Also, the gate electrode is composed of a Pt silicide film with a ratio of Si atoms to Pt atoms of approximately 1 (PtSix: x=1) in the vicinity of a region in contact with the gate insulator. Also, the gate electrode of the p channel MIS transistor is composed of a Pt silicide film with a ratio of Si atoms to Pt atoms of less than 1 (PtSix: x

    摘要翻译: 提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪膜组成。 此外,栅电极由与栅极接触的区域附近的Si原子与Pt原子的比率为约1(PtSi x x:x = 1)的Pt硅化物膜构成 绝缘子。 此外,p沟道MIS晶体管的栅电极由Si原子与Pt原子的比例小于1(PtSi x x:x <1)的Pt硅化物膜组成, 与栅极绝缘体接触的区域。 因此,抑制了栅电极的费米能级钉扎。

    Semiconductor device and manufacturing method thereof
    19.
    发明申请
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号:US20050280095A1

    公开(公告)日:2005-12-22

    申请号:US11132373

    申请日:2005-05-19

    摘要: The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a gate electrode of a p channel MISFET is composed of a nickel-silicon-germanium film formed by reacting a nondope silicon germanium film with the Ni film. The work function of the gate electrode of the n channel MISFET is controlled by doping P, As, or Sb, and the work function of the gate electrode of the p channel MISFET is controlled by adjusting the Ge concentration.

    摘要翻译: 提高了半导体器件的性能和可靠性。 在具有CMISFET的半导体器件中,n沟道MISFET的栅电极由通过使掺杂有P,As或Sb的硅膜与Ni膜反应而形成的硅化镍膜,以及p沟道MISFET的栅电极 由通过非钝化硅锗膜与Ni膜反应形成的镍硅锗膜构成。 通过掺杂P,As或Sb来控制n沟道MISFET的栅电极的功函数,并且通过调整Ge浓度来控制p沟道MISFET的栅电极的功函数。