摘要:
The manufacturing process of a semiconductor device in which a n channel MIS transistor and a p channel MIS transistor each having a gate electrode made of a metal material formed on a gate insulator made of a high dielectric constant material are used to form a CMOS circuit is simplified. After simultaneously forming the gate electrodes of the n channel MIS transistor and the p channel MIS transistor by patterning a platinum film deposited on a gate insulator made of a hafnium oxide film, only the gate insulator on the side of the n channel MIS transistor is selectively reduced by using the catalytic reduction of the platinum film. By doing so, the work function of the gate electrode of the n channel MIS transistor is changed.
摘要:
A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.
摘要翻译:提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪(HfO 2 O 2)膜组成。 此外,n沟道MIS晶体管的栅电极由Ni(镍)硅化物膜构成,p沟道MIS晶体管的栅电极由Pt(铂)膜构成。 在这种结构中,可以防止栅电极的费米能级钉扎。 因此,可以抑制n沟道MIS晶体管和p沟道MIS晶体管的阈值电压的增加。
摘要:
A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.
摘要翻译:提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪(HfO 2 O 2)膜组成。 此外,n沟道MIS晶体管的栅电极由Ni(镍)硅化物膜构成,p沟道MIS晶体管的栅电极由Pt(铂)膜构成。 在这种结构中,可以防止栅电极的费米能级钉扎。 因此,可以抑制n沟道MIS晶体管和p沟道MIS晶体管的阈值电压的增加。
摘要:
The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is comprised of metal silicide containing Ni, metal with a work function lower than that of Ni, and Si, and a gate electrode of a p channel MISFET is comprised of metal silicide containing Ni, metal with a work function higher than that of Ni, and Si. Since metal with a work function lower than that of Ni is contained in the gate electrode of the n channel MISFET and metal with a work function higher than that of Ni is contained in the gate electrode of the p channel MISFET, the threshold voltage can be reduced in both the n channel MISFET and the p channel MISFET. Also, the gate electrodes are formed by reacting a nondope silicon film with a metal film.
摘要:
In a semiconductor device and production method thereof, a technique is used to prevent film separation of the bottom electrode occurring during a heat treatment process which is carried out to make the bottom electrode closely packed and in the heat treatment process for producing dielectric crystallization. In the production method, a glue layer including an insulator is formed between SiO2 insulation layer and the inner wall of a concave hole. The SiO2 layer 14 is located on the Si board 11, and Si plug 12 and a barrier layer 13 are formed therein. A glue layer 16 is formed on the inner wall of the hole of the SiO2 insulation layer 15, and a bottom electrode 17 comprising Ru is formed on the barrier layer 13 and glue layer 16. Dielectric film 18 comprising BST and a top electrode 19 comprising Ru are laminated sequentially on the bottom electrode 17, to form a dielectric device with the bottom electrode 17.
摘要:
The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a gate electrode of a p channel MISFET is composed of a nickel-silicon-germanium film formed by reacting a nondope silicon germanium film with the Ni film. The work function of the gate electrode of the n channel MISFET is controlled by doping P, As, or Sb, and the work function of the gate electrode of the p channel MISFET is controlled by adjusting the Ge concentration.
摘要:
As shown in FIG. 2B, a gate electrode is formed on a gate insulating film on a semiconductor substrate. A high dielectric film with a dielectric constant higher than that of a silicon oxide film is used for the gate insulating film, and a platinum-rich silicide film is used for the gate electrode. The platinum-rich silicide film indicates a film with a ratio of silicon atoms to platinum atoms of less than 1 (PtSix: x
摘要:
A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of a n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide film. Also, the gate electrode is composed of a Pt silicide film with a ratio of Si atoms to Pt atoms of approximately 1 (PtSix: x=1) in the vicinity of a region in contact with the gate insulator. Also, the gate electrode of the p channel MIS transistor is composed of a Pt silicide film with a ratio of Si atoms to Pt atoms of less than 1 (PtSix: x
摘要翻译:提供了用于实现能够同时实现高导通电流和低功耗的CMOS电路的MIS晶体管的结构。 n沟道MIS晶体管和p沟道MIS晶体管的每个栅绝缘体由氧化铪膜组成。 此外,栅电极由与栅极接触的区域附近的Si原子与Pt原子的比率为约1(PtSi x x:x = 1)的Pt硅化物膜构成 绝缘子。 此外,p沟道MIS晶体管的栅电极由Si原子与Pt原子的比例小于1(PtSi x x:x <1)的Pt硅化物膜组成, 与栅极绝缘体接触的区域。 因此,抑制了栅电极的费米能级钉扎。
摘要:
The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a gate electrode of a p channel MISFET is composed of a nickel-silicon-germanium film formed by reacting a nondope silicon germanium film with the Ni film. The work function of the gate electrode of the n channel MISFET is controlled by doping P, As, or Sb, and the work function of the gate electrode of the p channel MISFET is controlled by adjusting the Ge concentration.
摘要:
After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.