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    Semiconductor integrated circuit device
    12.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20060291110A1

    公开(公告)日：2006-12-28

    申请号：US11447168

    申请日：2006-06-06

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

    IPC分类号： H02H7/00

    CPC分类号： H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device is provided, the circuit being capable of arranging a control signal system, avoiding a danger of failure to check an indefinite signal propagation prevention circuit or the like, further facilitating a check oriented to mounting on an automated tool, and facilitating power shutdown control inside of a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains Area A to Area I. A rule is provided, the rule defining that, in the case where a circuit having a high priority is turned ON, a power domain having its lower priority cannot be turned OFF, thereby facilitating a designing method. In addition, areas capable of applying still another power supply are provided in the independent power areas Area A to Area I. In that area, a relay buffer (repeater) and a clock buffer or an information retaining latch for saving information are integrated. A layout may be provided in a direction vertical to a direction in which cells are arranged in a row direction for the purpose of dispersing a current of a light supply line.

    摘要翻译： 提供了一种半导体集成电路器件，该电路能够布置控制信号系统，避免不能检查不确定的信号传播防止电路等的危险，进一步便于针对安装在自动化工具上的检查，并且促进 功率关断控制芯片内部。 在半导体集成电路装置中，功率关闭优先级由独立的电源区域A至区域I提供。规定了在具有高优先级的电路被接通的情况下，规定了具有 其较低优先级不能关闭，从而有助于设计方法。 此外，在独立电源区域A至区域I中提供能够应用另一电源的区域。在该区域中，集成了用于保存信息的中继缓冲器（中继器）和时钟缓冲器或信息保持锁存器。 为了分散供电线的电流，布置可以沿垂直于单元布置在行方向上的方向设置。

    Semiconductor integrated circuit device
    13.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08063691B2

    公开(公告)日：2011-11-22

    申请号：US13020169

    申请日：2011-02-03

    申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

    发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

    IPC分类号： H03L5/00

    CPC分类号： H03K19/0016 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

    摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。

    Semiconductor integrated circuit device
    14.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20060091942A1

    公开(公告)日：2006-05-04

    申请号：US11296442

    申请日：2005-12-08

    申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

    发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

    IPC分类号： H01L25/00

    CPC分类号： H03K19/0016 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

    摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO 1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO 1〜MIO 4）通常用于连接电路块。

    Semiconductor integrated circuit and control method for clock signal synchronization
    18.
    发明授权
    Semiconductor integrated circuit and control method for clock signal synchronization 失效
    半导体集成电路和时钟信号同步控制方法

    公开(公告)号：US08183899B2

    公开(公告)日：2012-05-22

    申请号：US12615607

    申请日：2009-11-10

    申请人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

    发明人： Yusuke Kanno ,  Makoto Saen ,  Shigenobu Komatsu ,  Masafumi Onouchi

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0814 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H03L7/0818 ,  H03L7/089 ,  Y02D10/126 ,  Y02D10/172

    摘要： There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

    摘要翻译： 在对区域进行电源电压变化的情况下，需要以低成本和高精度地确保DVFS控制下的电路区域的操作性能。 第一电路（FVA）使用第一电源电压（VDDA）进行操作。 第二电路（NFVA）使用第二电源电压（VDDB）进行操作。 可以在将时钟发送到这些电路的路径之间调整时钟延迟。 当VDDA等于VDDB时，通过不包含用于相位调整的延迟装置的路径将时钟分配给FVA。 当FVA区域的电源电压降低时，基于相当于时钟位移的一个或两个周期的相位，将时钟分配给FVA区域。 提供同步控制以同步时钟（CKAF和CKBF）并确保操作，使得待比较的两个时钟的相位适合于设计值的范围，同时改变第一电路的电源电压。

    Semiconductor integrated circuit including power domains
    19.
    发明授权
    Semiconductor integrated circuit including power domains 有权
    半导体集成电路包括电源域

    公开(公告)号：US07954023B2

    公开(公告)日：2011-05-31

    申请号：US12342015

    申请日：2008-12-22

    申请人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

    发明人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

    IPC分类号： G01R31/28

    CPC分类号： H03K19/0016

    摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.

    摘要翻译： 提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。 半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN） 电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。 通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD
    20.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD 失效
    半导体集成电路和电路操作方法

    公开(公告)号：US20100301893A1

    公开(公告)日：2010-12-02

    申请号：US12787090

    申请日：2010-05-25

    申请人： Kazuo OTSUGA ,  Yusuke Kanno

    发明人： Kazuo OTSUGA ,  Yusuke Kanno

    IPC分类号： G01R31/26

    CPC分类号： G01R31/31721

    摘要： In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor. When the result data detected indicates the fast state, the power supply voltage VDD is set to a lower power supply voltage level “VDD−ΔVDD” corresponding to a small variation gradient “β[V/σ]”. When the result data detected indicates the typical state, the power supply voltage VDD is set to an intermediate power supply voltage level “VDD±0”. When the result data detected indicates the slow state, the power supply voltage VDD is set to a higher power supply voltage level “VDD+ΔVDD” corresponding to a large variation gradient “α[V/σ]”.

    摘要翻译： 在其中低阈值电压和高阈值电压晶体管被混合地布置的半导体集成电路中，通过调节电源电压VDD可以在速度控制执行中适当地控制每个晶体管的工作速度。 半导体集成电路包括内部电路和测量电路。 内部电路包括低阈值电压MOS晶体管和高阈值电压MOS晶体管，并且低阈值电压MOS晶体管的阈值电压变化程度大于高阈值电压MOS晶体管的阈值电压变化的程度 阈值电压MOS晶体管。 测量电路检测低阈值电压MOS晶体管和高阈值电压MOS晶体管中的哪一个快速，典型和慢速状态。 当检测到的结果数据指示快速状态时，电源电压VDD被设置为对应于小变化梯度“＆bgr; [V /＆sgr]]的较低电源电压电平”VDD-＆Dgr; VDD“。 当检测到的结果数据表示典型状态时，将电源电压VDD设定为中间电源电压电平“VDD±0”。 当检测到的结果数据表示慢速状态时，将电源电压VDD设定为与较大变化梯度“α[V /＆sgr”]对应的较高电源电压电平“VDD +＆Dgr; VDD”。