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    Semiconductor structure and method for forming the same
    14.
    发明授权
    Semiconductor structure and method for forming the same 有权

    公开(公告)号：US11659772B2

    公开(公告)日：2023-05-23

    申请号：US17705404

    申请日：2022-03-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

    IPC: H10N50/01 ,  H01L23/544 ,  H10B61/00 ,  H10N50/80

    CPC classification number: H10N50/01 ,  H01L23/544 ,  H10B61/00 ,  H10N50/80 ,  H01L2223/54426

    Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.

    Semiconductor device and manufacturing method thereof
    16.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11522127B2

    公开(公告)日：2022-12-06

    申请号：US17204937

    申请日：2021-03-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chen-Yi Weng ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Chin-Yang Hsieh

    IPC: H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
    18.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20220310697A1

    公开(公告)日：2022-09-29

    申请号：US17228720

    申请日：2021-04-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

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