公开(公告)号：US09691901B2

公开(公告)日：2017-06-27

申请号：US14873214

申请日：2015-10-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Man-Ling Lu ,  I-Fan Chang ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L21/823814 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.

公开(公告)号：US20240373754A1

公开(公告)日：2024-11-07

申请号：US18203642

申请日：2023-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Po-Kai hsu

IPC: H10N50/01 ,  H10N50/80

Abstract: The invention provides a semiconductor structure, which comprises a plurality of magnetic tunnel junction (MTJ) elements. Seen from a top view, the MTJ elements are arranged in an array, at least one second contact structure is located in the array arranged by the MTJ elements, and at least one first mask layer covers a top surface and two sidewalls of each MTJ element, when seen from a cross-sectional view, a sidewall of the first mask layer is aligned with a sidewall of a second metal layer which is disposed below the second contact structure.

公开(公告)号：US11665978B2

公开(公告)日：2023-05-30

申请号：US16930291

申请日：2020-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.

公开(公告)号：US20210305316A1

公开(公告)日：2021-09-30

申请号：US16857152

申请日：2020-04-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  G11C11/16 ,  H01F41/34 ,  H01F10/32

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.

公开(公告)号：US20210135092A1

公开(公告)日：2021-05-06

申请号：US16698924

申请日：2019-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Hung-Yueh Chen ,  Yu-Ping Wang ,  Jia-Rong Wu ,  Rai-Min Huang ,  Ya-Huei Tsai ,  I-Fan Chang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate and a dummy MTJ between the first MTJ and the second MTJ, in which a bottom surface of the dummy MTJ is not connected to any metal. Preferably, the semiconductor device further includes a first metal interconnection under the first MTJ, a second metal interconnection under the second MTJ, and a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection and directly under the dummy MTJ.

公开(公告)号：US10468493B2

公开(公告)日：2019-11-05

申请号：US16212626

申请日：2018-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ting Chiang ,  Chi-Ju Lee ,  Chih-Wei Lin ,  Bo-Yu Su ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/51

Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.

公开(公告)号：US10388749B2

公开(公告)日：2019-08-20

申请号：US16043120

申请日：2018-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang ,  Chun-Ting Chiang ,  Chih-Wei Lin ,  Bo-Yu Su ,  Chi-Ju Lee

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/06 ,  H01L29/49 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.

公开(公告)号：US20180358448A1

公开(公告)日：2018-12-13

申请号：US15641312

申请日：2017-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ting Chiang ,  Chi-Ju Lee ,  Chih-Wei Lin ,  Bo-Yu Su ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/4975 ,  H01L21/02074 ,  H01L21/28088

Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.

公开(公告)号：US20240365677A1

公开(公告)日：2024-10-31

申请号：US18329588

申请日：2023-06-06

Applicant: United Microelectronics Corp.

Inventor： Jia-Rong Wu ,  Yi-An Shih ,  Hsiu-Hao Hu ,  I-Fan Chang ,  Rai-Min Huang ,  Po Kai Hsu

IPC: H10N50/20 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/20 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80

Abstract: Provided is a semiconductor device including a substrate, a first interconnection structure, and an MTJ device. The first interconnection structure is disposed on the substrate. The MTJ device is reversely bonded to the first interconnection structure. The MTJ device includes a first electrode layer, a second electrode layer and an MTJ stack structure. The first electrode layer is bonded to the first interconnect structure. The second electrode layer is located above the first electrode layer. The MTJ stack structure is located between the first and second electrode layers. The MTJ stack structure includes a first barrier layer, a free layer and a reference layer. The first barrier layer is located between the first and second electrode layers. The free layer is located between the first barrier layer and the first electrode layer. The reference layer is located between the first barrier layer and the second electrode layer.

公开(公告)号：US12052932B2

公开(公告)日：2024-07-30

申请号：US18132989

申请日：2023-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.