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公开(公告)号：US11637233B2
公开(公告)日：2023-04-25
申请号：US17086447
申请日：2020-11-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Si-Han Tsai , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Ju-Chun Fan , Ching-Hua Hsu , Yi-Yu Lin , Hung-Yueh Chen
Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
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公开(公告)号：US20220392954A1
公开(公告)日：2022-12-08
申请号：US17888451
申请日：2022-08-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H01L27/22 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H01L43/02 , H01L43/12
Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.
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公开(公告)号：US20220336735A1
公开(公告)日：2022-10-20
申请号：US17857185
申请日：2022-07-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Wei Chen , Po-Kai Hsu , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
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公开(公告)号：US11417838B2
公开(公告)日：2022-08-16
申请号：US16884060
申请日：2020-05-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Wei Chen , Po-Kai Hsu , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
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公开(公告)号：US11387408B2
公开(公告)日：2022-07-12
申请号：US17131767
申请日：2020-12-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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Patent Agency Ranking
16.发明授权公开(公告)号：US11309486B2
公开(公告)日：2022-04-19
申请号：US16719992
申请日：2019-12-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.
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公开(公告)号：US20220102621A1
公开(公告)日：2022-03-31
申请号：US17086447
申请日：2020-11-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Si-Han Tsai , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Ju-Chun Fan , Ching-Hua Hsu , Yi-Yu Lin , Hung-Yueh Chen
Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
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公开(公告)号：US20210343786A1
公开(公告)日：2021-11-04
申请号：US16882783
申请日：2020-05-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号：US20210296572A1
公开(公告)日：2021-09-23
申请号：US17341417
申请日：2021-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
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公开(公告)号：US11087812B1
公开(公告)日：2021-08-10
申请号：US16931438
申请日：2020-07-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Hui Lee , I-Ming Tseng , Chiu-Jung Chiu , Chung-Liang Chu , Yu-Chun Chen , Ya-Sheng Feng , Yi-An Shih , Hsiu-Hao Hu , Yu-Ping Wang
Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.
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