公开(公告)号：US09449960B2

公开(公告)日：2016-09-20

申请号：US13937142

申请日：2013-07-08

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang

IPC: H01L21/70 ,  H01L27/02

CPC classification number: H01L27/0277

Abstract: Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.

Abstract translation: 提供一种包括基板，拾取区域，第一MOS器件，第二MOS器件，第一掺杂区域和第二掺杂区域的静电放电（ESD）保护结构。 拾取区域位于基板中。 第一MOS器件具有位于衬底中的第一导电类型的第一漏极区域。 第二MOS器件具有位于衬底中的第一导电类型的第二漏极区域。 第一漏极区域比第二漏极区域更靠近拾取区域。 第二导电类型的第一掺杂区位于第一掺杂区的下方。 第二导电类型的第二掺杂区位于第二掺杂区的下方。 第一掺杂区域的面积和/或掺杂浓度大于第二掺杂区域的面积和/或掺杂浓度。

公开(公告)号：US09368500B2

公开(公告)日：2016-06-14

申请号：US14071670

申请日：2013-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Yu-Chun Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/092 ,  H01L29/78 ,  H01L27/06 ,  H01L27/02 ,  H01L21/8238

CPC classification number: H01L27/0925 ,  H01L21/823892 ,  H01L27/0274 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/785

Abstract: A CMOS device includes a substrate, a pMOS transistor and an nMOS transistor formed on the substrate, and a gated diode. The gated diode includes a floating gate formed on the substrate in between the pMOS transistor and the nMOS transistor and a pair of a p-doped region and an n-doped region formed in the substrate and between the pMOS transistor and the nMOS transistor. The n-doped region is formed between the floating gate and the nMOS transistor, and the p-doped region is formed between the floating gate and the pMOS transistor.

Abstract translation: CMOS器件包括衬底，pMOS晶体管和形成在衬底上的nMOS晶体管，以及门控二极管。 门控二极管包括形成在pMOS晶体管和nMOS晶体管之间的衬底上的浮置栅极和形成在衬底中以及在pMOS晶体管和nMOS晶体管之间的一对p掺杂区域和n掺杂区域。 在浮置栅极和nMOS晶体管之间形成n掺杂区域，并且在浮置栅极和pMOS晶体管之间形成p掺杂区域。

公开(公告)号：US09093565B2

公开(公告)日：2015-07-28

申请号：US13941555

申请日：2013-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L29/861 ,  H01L21/76 ,  H01L27/02

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

Abstract translation: 在本发明中提供了一种鳍式二极管结构及其制造方法，其结构包括：衬底，在衬底中形成的掺杂阱，多个第一导电类型的鳍和多个第二导电类型的鳍从 掺杂阱以及在第一导电类型的散热片，第二导电类型的散热片，浅沟槽隔离和掺杂阱之间的基板中全局形成的第一导电类型的掺杂区域，并与第一掺杂型的鳍片连接，以及 第二掺杂型散热片。

公开(公告)号：US08981521B1

公开(公告)日：2015-03-17

申请号：US13974939

申请日：2013-08-23

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Pei-Shan Tseng ,  Tien-Hao Tang

IPC: H01L29/735 ,  H01L29/73 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/861

Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.

Abstract translation: 提供了包括衬底，阱区，区域，至少一个轻掺杂区域，第一掺杂区域和第二掺杂区域的横向BJT。 衬底是第一导电类型。 阱区是第二导电类型并且在衬底中。 该地区在该地区。 至少一个轻掺杂区域位于该区域下方的阱区域中。 第一掺杂区域和第二掺杂区域是第一导电类型并且在该区域两侧的阱区域中。 第一掺杂区域连接到阴极。 第二掺杂区域连接到阳极，其中至少一个轻掺杂区域的掺杂浓度低于第一掺杂区域，第二掺杂区域和阱区域中的每一个的掺杂浓度。

公开(公告)号：US20150014809A1

公开(公告)日：2015-01-15

申请号：US13941555

申请日：2013-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/861 ,  H01L21/76

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

Abstract translation: 在本发明中提供了一种鳍式二极管结构及其制造方法，其结构包括：衬底，在衬底中形成的掺杂阱，多个第一导电类型的鳍和多个第二导电类型的鳍从 掺杂阱以及在第一导电类型的散热片，第二导电类型的散热片，浅沟槽隔离和掺杂阱之间的基板中全局形成的第一导电类型的掺杂区域，并与第一掺杂型的鳍片连接，以及 第二掺杂型散热片。

公开(公告)号：US09564436B2

公开(公告)日：2017-02-07

申请号：US14082529

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H02H9/04 ,  H01L27/092 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/092 ,  H01L27/0277 ,  H01L27/088

Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.

Abstract translation: 描述了一种半导体器件，包括包括第一区域和第二区域的衬底，第一区域中的第一导电类型的第一MOS元件和第二区域中的第一导电类型的第二MOS元件。 第一区域比第二区域更靠近基板的拾取区域。 衬底具有第二导电类型。 第一区域中的衬底中的第一导电通路的底部深度小于第二区域中的衬底中的第二导电通路的深度。

公开(公告)号：US09559091B2

公开(公告)日：2017-01-31

申请号：US14745458

申请日：2015-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.

Abstract translation: 制造鳍式二极管结构的方法包括提供衬底，在所述衬底中形成掺杂阱，在所述掺杂阱中形成至少一个第一导电类型的掺杂区或第二掺杂型的至少一个掺杂区，执行蚀刻工艺 到所述第一导电类型的掺杂区域或第二导电类型的所述掺杂区域，以在所述第一导电类型的掺杂区域上或在所述第二导电类型的所述掺杂区域上形成多个鳍片，在所述鳍片之间形成浅沟槽隔离，并执行 对所述翅片进行掺杂工艺以形成第一导电类型的鳍片和第二导电类型的鳍片。

公开(公告)号：US20150303183A1

公开(公告)日：2015-10-22

申请号：US14745458

申请日：2015-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L21/76 ,  H01L21/22 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type.

Abstract translation: 制造鳍式二极管结构的方法包括提供衬底，在所述衬底中形成掺杂阱，在所述掺杂阱中形成至少一个第一导电类型的掺杂区或第二掺杂型的至少一个掺杂区，执行蚀刻工艺 到所述第一导电类型的掺杂区域或第二导电类型的所述掺杂区域，以在所述第一导电类型的掺杂区域上或在所述第二导电类型的所述掺杂区域上形成多个鳍片，在所述鳍片之间形成浅沟槽隔离，并执行 对所述翅片进行掺杂工艺以形成第一导电类型的鳍片和第二导电类型的鳍片。

公开(公告)号：US20150221632A1

公开(公告)日：2015-08-06

申请号：US14687921

申请日：2015-04-16

Applicant: United Microelectronics Corp.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/78 ,  H01L27/06 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.

公开(公告)号：US08981488B1

公开(公告)日：2015-03-17

申请号：US14072976

申请日：2013-11-06

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Tien-Hao Tang ,  Chang-Tzu Wang

IPC: H01L21/70 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L21/823493

Abstract: A semiconductor structure and an integrated circuit are provided. The semiconductor structure includes a first field-effect transistor (FET), a second FET, an isolation structure, and a body electrode. The first FET includes a first active body having a first type conductivity. The second FET includes a second active body having the first type conductivity. The first active body and the second active body are isolated from each other by the isolation structure. The body electrode has the first type conductivity and formed in the second active body.

Abstract translation: 提供半导体结构和集成电路。 半导体结构包括第一场效应晶体管（FET），第二FET，隔离结构和体电极。 第一FET包括具有第一类型导电性的第一有源体。 第二FET包括具有第一类型导电性的第二有源体。 第一活性体和第二活性体通过隔离结构彼此隔离。 主体电极具有第一类型的导电性并且形成在第二主动体中。