公开(公告)号：US09780101B1

公开(公告)日：2017-10-03

申请号：US15361065

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Wenbo Ding ,  Xiaofei Han ,  Chien-Kee Pang ,  Yu-Yang Chen ,  Jubao Zhang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/788 ,  H01L27/11521 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.

公开(公告)号：US12278210B2

公开(公告)日：2025-04-15

申请号：US17883595

申请日：2022-08-08

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Kai Zhu ,  Chien-Kee Pang ,  Chia-Liang Liao

IPC: H01L21/00 ,  H01L21/02 ,  H01L23/00

Abstract: Provided is a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps. A first dielectric layer is formed on a first substrate. A second dielectric layer is formed on a second substrate. A first heat treatment is performed on the first dielectric layer and the second dielectric layer, wherein a temperature of the first heat treatment is between 300° C. and 400° C. A first conductive via is formed in the first dielectric layer. A second conductive via is formed in the second dielectric layer. The first substrate and the second substrate are bonded in a manner that the first dielectric layer faces the second dielectric layer, so as to connect the first conductive via and the second conductive via.

公开(公告)号：US12249607B2

公开(公告)日：2025-03-11

申请号：US18152781

申请日：2023-01-11

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Chunyuan Qi ,  Xingxing Chen ,  Chien-Kee Pang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

公开(公告)号：US20230411343A1

公开(公告)日：2023-12-21

申请号：US17883595

申请日：2022-08-08

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Kai Zhu ,  Chien-Kee Pang ,  Chia-Liang Liao

IPC: H01L23/00 ,  H01L21/02

CPC classification number: H01L24/80 ,  H01L21/02337 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Provided is a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps. A first dielectric layer is formed on a first substrate. A second dielectric layer is formed on a second substrate. A first heat treatment is performed on the first dielectric layer and the second dielectric layer, wherein a temperature of the first heat treatment is between 300° C. and 400° C. A first conductive via is formed in the first dielectric layer. A second conductive via is formed in the second dielectric layer. The first substrate and the second substrate are bonded in a manner that the first dielectric layer faces the second dielectric layer, so as to connect the first conductive via and the second conductive via.