公开(公告)号：US20160048072A1

公开(公告)日：2016-02-18

申请号：US14504401

申请日：2014-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hsien Tang ,  Yao-Jen Fan ,  Chin-Lung Lin

IPC: G03F1/70

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5081

Abstract: A layout pattern decomposition method includes following steps. A layout pattern is received. The layout pattern includes a plurality of features, and an edge-to-edge space is respectively defined in between two adjacent features. A sum of a width of the edge-to-edge space and a width of the feature on a left side of the edge-to-edge space and a sum of the width of the edge-to-edge space and a width of the feature on a right side of the edge-to-edge space are respectively calculated. The sums and a predetermined value are respectively compared. When any one of the sums is smaller than the predetermined value, the two features on the two sides of the edge-to-edge space are colored by a first color and alternatively a second color. The features including the first color are assigned to a first pattern and the features including the second color to a second pattern.

Abstract translation: 布局模式分解方法包括以下步骤。 接收到布局模式。 布局图案包括多个特征，并且在两个相邻特征之间分别限定边缘到边缘空间。 边缘至边缘空间的宽度和边缘至边缘空间的左侧上的特征的宽度的总和以及边缘至边缘空间的宽度和宽度之和 分别计算边缘到边缘空间右侧的特征。 分别对和值和预定值进行比较。 当总和中的任何一个小于预定值时，边缘到边缘空间的两侧上的两个特征被第一颜色和第二颜色着色。 包括第一颜色的特征被分配给第一图案，并且将包括第二颜色的特征分配给第二图案。

公开(公告)号：US09245822B2

公开(公告)日：2016-01-26

申请号：US14065412

申请日：2013-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hua Tsai ,  Jian-Cheng Chen ,  Chin-Yueh Tsai ,  Yao-Jen Fan ,  Heng-Kun Chen ,  Hsiang Yang

IPC: G03F1/36 ,  H01L23/48 ,  G06F17/50 ,  G03F1/70

CPC classification number: G03F1/70 ,  G06F17/5072 ,  G06F2217/12 ,  H01L21/0334 ,  H01L23/48 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.

Abstract translation: 半导体布局图案包括设备布局图案，具有第一尺寸的多个矩形第一虚设图案，具有变化的第二尺寸的多个矩形第二虚设图案以及比第二虚设图形小的多个第一通孔虚设图案， 在第二虚拟图案内的空间范围内。

公开(公告)号：US09009633B2

公开(公告)日：2015-04-14

申请号：US13887377

申请日：2013-05-06

Applicant: United Microelectronics Corp.

Inventor： Tsung-Yeh Wu ,  Chin-Lung Lin ,  Yao-Jen Fan ,  Wei-Han Chien ,  Chia-Chun Tsai

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.

Abstract translation: 一种校正辅助功能的方法包括以下步骤。 首先，由计算机系统接收第一布局图案，并且将第一布局图案分割成多个第一区域。 随后，将多个辅助特征添加到第一布局图案中以形成第二布局图案，其中与第一区域的任何边缘相邻的辅助特征中的至少一个被定义为所选择的图案。 然后，第二布局图案被分割成多个第二区域。 然后，对包括所选择的图案的第二区域执行检查步骤，并校正第二布局图案以形成校正的第二布局图案。