公开(公告)号：US20240105839A1

公开(公告)日：2024-03-28

申请号：US18528816

申请日：2023-12-05

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Ling-Chun Chou ,  Yu-Hung Chang ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L29/0623

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

公开(公告)号：US11881527B2

公开(公告)日：2024-01-23

申请号：US17472680

申请日：2021-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  Yu-Hung Chang ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L29/0623

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

公开(公告)号：US20230253497A1

公开(公告)日：2023-08-10

申请号：US18135198

申请日：2023-04-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  Te-Chi Yen ,  Yu-Hung Chang ,  Kun-Hsien Lee ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0653

Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

公开(公告)号：US20230052714A1

公开(公告)日：2023-02-16

申请号：US17472680

申请日：2021-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  Yu-Hung Chang ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/06

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

公开(公告)号：US09978745B2

公开(公告)日：2018-05-22

申请号：US15289988

申请日：2016-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ti Wang ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L27/082 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/082 ,  H01L27/0207 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0813 ,  H01L29/1008 ,  H01L29/407 ,  H01L29/735

Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.

公开(公告)号：US09502260B2

公开(公告)日：2016-11-22

申请号：US14599559

申请日：2015-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-An Huang ,  Kun-Hsien Lee

IPC: H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/3086 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure.

Abstract translation: 本发明提供了一种形成半导体结构的方法，包括：首先，提供基板，翅片结构设置在基板上，栅极结构与翅片结构交叉，第一硬掩模设置在第一硬掩模的顶表面上 门结构。 接下来，形成介电层，覆盖基板，翅片结构和栅极结构。 之后，在第一硬掩模的顶表面上形成第二硬掩模，其中第二硬掩模的宽度大于第一硬掩模的宽度，第二硬掩模的底面和第二硬掩模的顶表面 第一个硬面罩在同一水平上。 然后进行蚀刻处理以去除电介质的一部分和鳍结构的一部分。

公开(公告)号：US20160189970A1

公开(公告)日：2016-06-30

申请号：US14599559

申请日：2015-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-An Huang ,  Kun-Hsien Lee

IPC: H01L21/308 ,  H01L29/78

CPC classification number: H01L21/3081 ,  H01L21/3086 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure.

Abstract translation: 本发明提供了一种形成半导体结构的方法，包括：首先，提供基板，翅片结构设置在基板上，栅极结构与翅片结构交叉，第一硬掩模设置在第一硬掩模的顶表面上 门结构。 接下来，形成介电层，覆盖基板，翅片结构和栅极结构。 之后，在第一硬掩模的顶表面上形成第二硬掩模，其中第二硬掩模的宽度大于第一硬掩模的宽度，第二硬掩模的底面和第二硬掩模的顶表面 第一个硬面罩在同一水平上。 然后进行蚀刻处理以去除电介质的一部分和鳍结构的一部分。

公开(公告)号：US11664450B2

公开(公告)日：2023-05-30

申请号：US17216642

申请日：2021-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ling-Chun Chou ,  Te-Chi Yen ,  Yu-Hung Chang ,  Kun-Hsien Lee ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/086 ,  H01L29/0878

Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

公开(公告)号：US11488870B2

公开(公告)日：2022-11-01

申请号：US16843880

申请日：2020-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Hsieh ,  Kuan-Ti Wang ,  Han-Chen Chen ,  Kun-Hsien Lee

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L29/49 ,  H01L21/3105

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.

公开(公告)号：US20210287942A1

公开(公告)日：2021-09-16

申请号：US16843880

申请日：2020-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Yu Hsieh ,  Kuan-Ti Wang ,  Han-Chen Chen ,  Kun-Hsien Lee

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/321 ,  H01L29/49 ,  H01L21/28

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a first gate structure on the first region, a second gate structure on the second region, and a third gate structure on the third region; forming an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure; removing the first gate structure, the second gate structure, and the third gate structure to form a first recess, a second recess, and a third recess; forming a first interfacial layer in the first recess, the second recess, and the third recess; removing the first interfacial layer in the second recess; and forming a second interfacial layer in the second recess.