公开(公告)号：US10262940B2

公开(公告)日：2019-04-16

申请号：US15667637

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/522

Abstract: An electric connector includes a metal interconnect, a first vertical element and a second vertical element. The metal interconnect includes a plurality of horizontal elements. The first vertical element physically connects to a top surface of each of the horizontal elements. The second vertical element physically connects to a bottom surface of each of the horizontal elements, and the second vertical element misaligns the first vertical element. The present invention also provides an electric connector including a first vertical element and a second vertical element. The first vertical element physically connects to a top surface of a horizontal element. The second vertical element physically connects to a bottom surface of the horizontal element, and the second vertical element misaligns the first vertical element, wherein the first vertical element or the horizontal element is burned out before the second vertical element is burned out while a voltage is applied.

公开(公告)号：US20180138166A1

公开(公告)日：2018-05-17

申请号：US15351413

申请日：2016-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7835

Abstract: A semiconductor device for ESD protection, includes a drain region, a first doped region, a second doped region and a source region. The drain region is disposed in a substrate at a first side of a gate and the drain region has a first conductivity type. The first doped region is disposed in a second doped well at a second side of the gate and has a second conductivity type. The source region is also disposed in the second doped well and has the first conductive type, and the source region surrounds the first doped region from a topview. The second doped region is disposed in the second doped well and has the second conductive type, and the second doped region is disposed between the gate and the source region, wherein a plurality of contacts is electrically connected to the second doped region.

公开(公告)号：US09859271B2

公开(公告)日：2018-01-02

申请号：US15007163

申请日：2016-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wei Lee ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/06

CPC classification number: H01L27/0262 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/7436 ,  H01L29/861

Abstract: An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.

公开(公告)号：US09793258B1

公开(公告)日：2017-10-17

申请号：US15344212

申请日：2016-11-04

Applicant: United Microelectronics Corp.

Inventor： Cheng-Te Lin ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  H01L27/0259 ,  H01L27/0288

Abstract: An electrostatic discharge device includes a substrate. A deep doped well of a first conductive type is disposed in the substrate. A drain doped well of the first conductive type is disposed in the substrate above the deep doped well. An inserted doping well of a second conductive type is disposed in the drain doped well, in contact with the deep doped well. A drain region of the first conductive type is in the drain doped well and above the inserted doping well. An inserted drain of the second conductive type is on the inserted doping well and surrounded by the drain region. A source doped well of the second conductive type is disposed in the substrate, abut the drain doped well. A source region is disposed in the source doped well. A gate structure is disposed on the substrate between the drain region and the source region.

公开(公告)号：US20170213818A1

公开(公告)日：2017-07-27

申请号：US15481444

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0255 ,  H01L27/0288 ,  H02H9/046

Abstract: The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

公开(公告)号：US08896024B1

公开(公告)日：2014-11-25

申请号：US13940081

申请日：2013-07-11

Applicant: United Microelectronics Corp.

Inventor： Yi-Chun Chen ,  Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7412 ,  H01L29/7436 ,  H01L29/87

Abstract: Provided is an electrostatic discharge (ESD) protection structure including a first and a second well region adjacent to each other, a first and a second doped region disposed in the first well region, a fourth and a fifth doped region disposed in the second well region, and a third doped region disposed in the first region and extending into the second well region. The second doped region is disposed between the first and the third doped regions, forming a diode with the first doped region, forming, together with the first well region and the second well region, a first bipolar junction transistor (BJT) electrically connecting to the diode, and having no contact window disposed thereon. The fourth doped region is disposed between the third and the fifth doped regions, forming a second BJT with the second well region and the first well region.

Abstract translation: 提供一种静电放电（ESD）保护结构，其包括彼此相邻的第一和第二阱区，设置在第一阱区中的第一和第二掺杂区，设置在第二阱区中的第四和第五掺杂区 以及设置在第一区域中并延伸到第二阱区域中的第三掺杂区域。 第二掺杂区域设置在第一和第三掺杂区域之间，形成具有第一掺杂区域的二极管，与第一阱区域和第二阱区域一起形成电连接到第一掺杂区域的第一双极结型晶体管（BJT） 二极管，并且没有布置在其上的接触窗口。 第四掺杂区域设置在第三和第五掺杂区域之间，与第二阱区域和第一阱区域形成第二BJT。

公开(公告)号：US09876006B2

公开(公告)日：2018-01-23

申请号：US15188962

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yu Tai ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0277 ,  H01L29/0623 ,  H01L29/0653

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. The drain region is disposed in the doped well and has a second conductive type. The source region is disposed in the doped well and has the second conductive type, wherein the source region is separated from the drain region. The doped region is disposed in the doped well between the drain region and the source region, wherein the doped region has the first conductive type and is in contact with the doped well and the source region. The guard ring is disposed in the doped well and has the first conductive type.

公开(公告)号：US09691754B2

公开(公告)日：2017-06-27

申请号：US14691126

申请日：2015-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Yi-Chun Chen ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36

CPC classification number: H01L27/0266 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36

Abstract: A semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The first lightly doped region is disposed in the well. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The first heavily doped region is disposed in the first lightly doped region. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region. The well has a first doping type. The first lightly doped region, the second lightly doped region, the first heavily doped region and the second heavily doped region have a second doping type.

公开(公告)号：US09613948B1

公开(公告)日：2017-04-04

申请号：US15273682

申请日：2016-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Ming Wang ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/00 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/7835

Abstract: An ESD protection semiconductor device includes a substrate, a first isolation structure formed in the substrate, a gate disposed on the substrate, a source region formed in the substrate a first side of the gate, a first doped region formed in the substrate at a second side of the gate opposite to the first side, and a drain region formed in the first doped region. The gate overlaps a portion of the first isolation structure. The drain region is spaced apart from the first isolation by a portion of the first doped region. The substrate includes a first conductivity type, the source region, and the first doped region and the drain region include a second conductivity type. And the second conductivity type is complementary to the first conductivity type.

公开(公告)号：US20170084602A1

公开(公告)日：2017-03-23

申请号：US14920902

申请日：2015-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Cih Wang ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8249 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/8249 ,  H01L27/027 ,  H01L29/1095 ,  H01L29/78 ,  H01L29/7816

Abstract: An electrostatic discharge protection device includes an anode, a cathode, a negative voltage holding transistor and a positive voltage holding transistor. The anode is coupled to an input terminal, and the cathode is coupled to a ground. The negative voltage holding transistor includes an N-well. The positive voltage holding transistor includes an N-well. The N-well of the positive voltage holding transistor and the N-well of the negative voltage holding transistor are coupled together and are float. The negative voltage holding transistor and the positive voltage holding transistor are coupled between the anode and the cathode in a manner of back-to-back.