公开(公告)号：US20220093584A1

公开(公告)日：2022-03-24

申请号：US17075707

申请日：2020-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252

Abstract: A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.

公开(公告)号：US09640527B2

公开(公告)日：2017-05-02

申请号：US14728053

申请日：2015-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ting Lin ,  Yi-Chun Chen ,  Tien-Hao Tang

IPC: H01L21/8234 ,  H01L23/58 ,  H01L27/02

CPC classification number: H01L27/0274 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/861

Abstract: An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.

公开(公告)号：US20160293593A1

公开(公告)日：2016-10-06

申请号：US14691126

申请日：2015-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Yi-Chun Chen ,  Li-Cih Wang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/08 ,  H01L29/36 ,  H01L29/10

CPC classification number: H01L27/0266 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36

Abstract: A semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The first lightly doped region is disposed in the well. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The first heavily doped region is disposed in the first lightly doped region. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region. The well has a first doping type. The first lightly doped region, the second lightly doped region, the first heavily doped region and the second heavily doped region have a second doping type.

Abstract translation: 半导体结构包括阱，第一轻掺杂区，第二轻掺杂区，第一重掺杂区，第二重掺杂区和栅极。 第一轻掺杂区域设置在阱中。 第二轻掺杂区域设置在阱中并与第一轻掺杂区域分离。 第一重掺杂区域设置在第一轻掺杂区域中。 第二重掺杂区域部分地设置在第二轻掺杂区域中。 第二重掺杂区域具有接触阱的表面。 栅极设置在第一重掺杂区域和第二重掺杂区域之间的阱上。 该井具有第一种掺杂型。 第一轻掺杂区域，第二轻掺杂区域，第一重掺杂区域和第二重掺杂区域具有第二掺杂类型。

公开(公告)号：US20230223399A1

公开(公告)日：2023-07-13

申请号：US18119253

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L29/778 ,  H01L29/205 ,  H01L21/306 ,  H01L29/40 ,  H01L21/765 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L27/0605 ,  H01L29/7786 ,  H01L29/205 ,  H01L21/30621 ,  H01L29/402 ,  H01L27/0629 ,  H01L21/765 ,  H01L21/8252 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/66462

Abstract: A resistor with GaN structures, including a GaN layer with a 2DEG resistor region and an undoped polysilicon resistor region, an AlGaN barrier layer on the GaN layer in the 2DEG resistor region, multiple p-type doped GaN capping layers arranged on the AlGaN barrier layer so that the GaN layer not covered by the p-type doped GaN capping layers in the 2DEG resistor region is converted into a 2DEG resistor, a passivation layer on the GaN layer, and an undoped polysilicon layer on the passivation layer in the undoped polysilicon resistor region and functions as an undoped polysilicon resistor.

公开(公告)号：US11631664B2

公开(公告)日：2023-04-18

申请号：US17075707

申请日：2020-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252

Abstract: A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.

公开(公告)号：US08896024B1

公开(公告)日：2014-11-25

申请号：US13940081

申请日：2013-07-11

Applicant: United Microelectronics Corp.

Inventor： Yi-Chun Chen ,  Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7412 ,  H01L29/7436 ,  H01L29/87

Abstract: Provided is an electrostatic discharge (ESD) protection structure including a first and a second well region adjacent to each other, a first and a second doped region disposed in the first well region, a fourth and a fifth doped region disposed in the second well region, and a third doped region disposed in the first region and extending into the second well region. The second doped region is disposed between the first and the third doped regions, forming a diode with the first doped region, forming, together with the first well region and the second well region, a first bipolar junction transistor (BJT) electrically connecting to the diode, and having no contact window disposed thereon. The fourth doped region is disposed between the third and the fifth doped regions, forming a second BJT with the second well region and the first well region.

Abstract translation: 提供一种静电放电（ESD）保护结构，其包括彼此相邻的第一和第二阱区，设置在第一阱区中的第一和第二掺杂区，设置在第二阱区中的第四和第五掺杂区 以及设置在第一区域中并延伸到第二阱区域中的第三掺杂区域。 第二掺杂区域设置在第一和第三掺杂区域之间，形成具有第一掺杂区域的二极管，与第一阱区域和第二阱区域一起形成电连接到第一掺杂区域的第一双极结型晶体管（BJT） 二极管，并且没有布置在其上的接触窗口。 第四掺杂区域设置在第三和第五掺杂区域之间，与第二阱区域和第一阱区域形成第二BJT。

公开(公告)号：US20240429228A1

公开(公告)日：2024-12-26

申请号：US18829265

申请日：2024-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A method of manufacturing a resistor-transistor-logic circuit with GaN structures, including steps of forming a GaN layer, an AlGaN barrier layer and a p-type doped GaN capping layer on a substrate, patterning the p-type doped GaN capping layer into multiple p-type doped GaN capping patterns, wherein the GaN layer under parts of the p-type doped GaN capping patterns is converted into gate depletion regions, and the GaN layer not covered by the p-type doped GaN capping patterns in a resistor region functions as 2DEG resistors, forming a passivation layer on the GaN layer and the p-type doped GaN capping patterns, forming multiple sources and drains on the GaN layer, and forming multiple gates on the p-type doped GaN capping patterns, wherein the gates, sources and drains in a high-voltage device region constitute high-voltage HEMTs, and the gates, sources and drains in a low-voltage device region constitute low-voltage logic FETs.

公开(公告)号：US12132043B2

公开(公告)日：2024-10-29

申请号：US18119260

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02

CPC classification number: H01L27/0605 ,  H01L21/30621 ,  H01L21/765 ,  H01L21/8252 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

公开(公告)号：US20230223400A1

公开(公告)日：2023-07-13

申请号：US18119260

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L29/778 ,  H01L21/306 ,  H01L29/205 ,  H01L21/765 ,  H01L29/40 ,  H01L21/8252 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L27/0605 ,  H01L21/765 ,  H01L21/8252 ,  H01L21/30621 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/205 ,  H01L29/402 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/66462

Abstract: A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

公开(公告)号：US20160358904A1

公开(公告)日：2016-12-08

申请号：US14728053

申请日：2015-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ting Lin ,  Yi-Chun Chen ,  Tien-Hao Tang

IPC: H01L27/02

CPC classification number: H01L27/0274 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/861

Abstract: An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.

Abstract translation: 静电放电（ESD）保护装置包括第一触发元件和第一硅控制整流器（SCR）元件。 第一触发元件具有形成在衬底中的第一寄生双极结型晶体管（BJT）。 第一SCR元件在衬底中形成第二寄生BJT。 第一寄生BJT和第二寄生BJT具有公共寄生双极基极，并且第一寄生BJT的触发电压基本上低于第二寄生BJT的触发电压。