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    LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY
    11.
    发明申请
    LAYOUT PATTERN FOR STATIC RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20240404587A1

    公开(公告)日：2024-12-05

    申请号：US18218025

    申请日：2023-07-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Chun-Yen Tseng

    IPC: G11C11/412 ,  G11C5/06

    Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

    Layout pattern of static random access memory
    12.
    发明授权
    Layout pattern of static random access memory 有权

    公开(公告)号：US12148809B2

    公开(公告)日：2024-11-19

    申请号：US17583225

    申请日：2022-01-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

    IPC: H01L29/423 ,  G11C5/06 ,  G11C11/412 ,  H01L29/78 ,  H10B10/00

    Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

    Static random access memory array pattern
    13.
    发明公开
    Static random access memory array pattern 审中-公开

    公开(公告)号：US20230403837A1

    公开(公告)日：2023-12-14

    申请号：US17857065

    申请日：2022-07-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Chun-Yen Tseng

    IPC: H01L27/11

    CPC classification number: H01L27/1104

    Abstract: The invention provides a static random access memory (SRAM) array pattern, which comprises a substrate, a first region, a second region, a third region and a fourth region are defined on the substrate and arranged in an array, each region partially overlaps with the other three regions, and each region contains a SRAM cell, the layout of the SRAM cell in the first region is the same as that in the third region, the layout of the SRAM cell in the second region is the same as that in the fourth region, and the layout of the SRAM cell in the first region and the layout of the SRAM cell in the fourth region are mirror patterns along a horizontal axis.

    Layout pattern of static random access memory
    14.
    发明申请
    Layout pattern of static random access memory 有权

    公开(公告)号：US20250095724A1

    公开(公告)日：2025-03-20

    申请号：US18966047

    申请日：2024-12-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu- Feng Chang ,  Chun-Chieh Chang

    IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

    Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

    STATIC RANDOM ACCESS MEMORY STRUCTURE
    18.
    发明申请
    STATIC RANDOM ACCESS MEMORY STRUCTURE 审中-公开

    公开(公告)号：US20190096892A1

    公开(公告)日：2019-03-28

    申请号：US16162340

    申请日：2018-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

    IPC: H01L27/11 ,  G11C11/412 ,  G11C7/18 ,  G11C8/14 ,  G11C5/06

    Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

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