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    ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE
    12.
    发明公开
    ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE 审中-公开

    公开(公告)号：US20230326919A1

    公开(公告)日：2023-10-12

    申请号：US17742392

    申请日：2022-05-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H01L27/02

    CPC classification number: H01L27/0259

    Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

    Semiconductor structure
    13.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US09691754B2

    公开(公告)日：2017-06-27

    申请号：US14691126

    申请日：2015-04-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Mei-Ling Chao ,  Yi-Chun Chen ,  Li-Cih Wang ,  Tien-Hao Tang

    IPC: H01L27/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36

    CPC classification number: H01L27/0266 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36

    Abstract: A semiconductor structure comprises a well, a first lightly doped region, a second lightly doped region, a first heavily doped region, a second heavily doped region and a gate. The first lightly doped region is disposed in the well. The second lightly doped region is disposed in the well and separated from the first lightly doped region. The first heavily doped region is disposed in the first lightly doped region. The second heavily doped region is partially disposed in the second lightly doped region. The second heavily doped region has a surface contacting the well. The gate is disposed on the well between the first heavily doped region and the second heavily doped region. The well has a first doping type. The first lightly doped region, the second lightly doped region, the first heavily doped region and the second heavily doped region have a second doping type.

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    15.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20140057403A1

    公开(公告)日：2014-02-27

    申请号：US14069179

    申请日：2013-10-31

    Applicant: United Microelectronics Corp.

    Inventor： Chang-Tzu Wang ,  Mei-Ling Chao ,  Chien-Ting Lin

    IPC: H01L29/66 ,  H01L21/265

    CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/823821 ,  H01L27/0924

    Abstract: A method for fabricating a semiconductor device is provided. A fin of a first conductivity type is formed on a substrate of the first conductivity type. A gate is formed on the substrate, wherein the gate covers a portion of the fin. Source and drain regions of a second conductivity type are formed in the fin at respective sides of the gate. A punch-through stopper (PTS) of the first conductivity type is formed in the fin underlying the gate and between the source and drain regions, wherein the PTS has an impurity concentration higher than that of the substrate. A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS.

    Abstract translation: 提供一种制造半导体器件的方法。 在第一导电类型的衬底上形成第一导电类型的鳍。 栅极形成在衬底上，其中栅极覆盖鳍片的一部分。 第二导电类型的源极和漏极区域形成在栅极的相应侧的翅片中。 第一导电类型的穿通止动件（PTS）形成在栅极下方的栅极和源极和漏极区域之间，其中PTS的杂质浓度高于衬底的杂质浓度。 将第二导电类型的第一杂质注入到PTS中，以补偿PTS的杂质浓度。

    ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    16.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE 有权

    公开(公告)号：US20250072042A1

    公开(公告)日：2025-02-27

    申请号：US18376450

    申请日：2023-10-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tzu-Hsin Chen ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-cheng Su

    IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

    Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

    Grounded gate NMOS transistor having source pulled back region
    17.
    发明授权
    Grounded gate NMOS transistor having source pulled back region 有权

    公开(公告)号：US10366978B1

    公开(公告)日：2019-07-30

    申请号：US16036914

    申请日：2018-07-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Hsiang Chang ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC: H01L27/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

    Abstract: A grounded gate NMOS transistor includes a P-type substrate, P-well region in the P-type substrate, and a gate finger traversing the P-well region. The gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall. An N+ drain doping region is disposed in the P-type substrate and is adjacent to the first sidewall of the gate finger. The N+ drain doping region is contiguous with a bottom edge of the first spacer. An N+ source doping region is disposed in the P-type substrate opposite to the N+ drain doping region. The N+ source doping region is kept a predetermined distance from a bottom edge of the second spacer. A P+ pick-up ring is disposed in the P-well region and surrounds the gate finger, the N+ drain doping region, and the N+ source doping region.

    Electrostatic discharge protection device
    18.
    发明授权
    Electrostatic discharge protection device 有权

    公开(公告)号：US10163895B2

    公开(公告)日：2018-12-25

    申请号：US15365602

    申请日：2016-11-30

    Applicant: United Microelectronics Corp.

    Inventor： Heng-Yu Lin ,  Kuei-Chih Fan ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang

    IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/40

    Abstract: An ESD protection device on a substrate includes a base doped region of a first conductivity type. A first inter doped region of a second conductivity type is in the base doped region. A drain region of the second conductivity type in the first inter doped region is connected to a first electrode terminal. An inserted doped region of the first conductivity type is in the drain region. A second inter doped region of the second conductivity type is in the base doped region. A source region of the second conductivity type is in the second inter doped region. A substrate-surface doped region of the first conductivity type in the substrate is adjacent to or in contact with the source region. A gate structure is between the drain and source regions in the substrate. The substrate-surface doped region and the source region are connected to a second electrode terminal.

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