公开(公告)号：US09136375B2

公开(公告)日：2015-09-15

申请号：US14085939

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

公开(公告)号：US20150137228A1

公开(公告)日：2015-05-21

申请号：US14085939

申请日：2013-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

公开(公告)号：US08829611B2

公开(公告)日：2014-09-09

申请号：US13629608

申请日：2012-09-28

Applicant: United Microelectronics Corp.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/78

CPC classification number: H01L29/0878 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7816

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 高电压金属氧化物半导体晶体管器件包括其中形成有绝缘区域的衬底，覆盖绝缘区域的一部分并形成在衬底上的栅极，形成在栅极各侧的源极区域和漏极区域 基板，形成在基板中并与栅极部分重叠的主体区域，以及形成在栅极下方并与主体区域相邻的基板中的第一注入区域。 衬底和体区包括第一导电类型。 源极区域，漏极区域和第一注入区域包括第二导电类型。 第一导电类型和第二导电类型彼此互补。

公开(公告)号：US09337802B2

公开(公告)日：2016-05-10

申请号：US14201914

申请日：2014-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu

IPC: H03H9/54 ,  H03H9/205 ,  H03H9/58

CPC classification number: H03H9/205 ,  H03H9/584 ,  H03H9/585 ,  H03H9/589

Abstract: A resonator filter includes a substrate, a bottom electrode formed on the substrate, a multi-layered coupling structure formed on the bottom electrode, a top electrode formed on the multi-layered coupling structure, a first piezoelectric layer sandwiched in between the bottom electrode and the multi-layered coupling structure, and a second piezoelectric layer sandwiched in between the multi-layered coupling structure and the top electrode. The multi-layered coupling structure includes at least an insulating material.

Abstract translation: 谐振器滤波器包括基板，形成在基板上的底部电极，形成在底部电极上的多层耦合结构，形成在多层耦合结构上的顶部电极，夹在底部电极和底部电极之间的第一压电层， 所述多层结合结构，以及夹在所述多层耦合结构和所述顶部电极之间的第二压电层。 多层结合结构至少包括绝缘材料。

公开(公告)号：US08921972B2

公开(公告)日：2014-12-30

申请号：US13896289

申请日：2013-05-16

Applicant: United Microelectronics Corp.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L21/70 ,  H01L29/78 ,  H01L27/092 ,  H01L27/085 ,  H01L27/088

CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 高压金属氧化物半导体（HV MOS）晶体管器件包括衬底，形成在衬底中的漂移区域，形成在漂移区域中并由漂移区域彼此分开的多个隔离结构，多个 分别形成在隔离结构中的掺杂岛，形成在衬底上的栅极，以及在栅极的相应两侧形成在衬底中的源极区和漏极区。 门覆盖每个隔离结构的一部分。 漂移区域，源区域和漏极区域包括第一导电类型，掺杂岛包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

公开(公告)号：US20140091369A1

公开(公告)日：2014-04-03

申请号：US13629609

申请日：2012-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/7816

Abstract: A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 提供HV MOS晶体管器件。 HV MOS晶体管器件包括至少包括形成在其上的绝缘区域的衬底，位于衬底上并覆盖绝缘区域的一部分的栅极，形成在衬底中的栅极的各个侧面处的漏极区域和源极区域， 以及形成在所述绝缘区域下方的第一注入区域。 衬底包括第一导电类型，漏极，源极和第一注入区域包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。