公开(公告)号：US20170162721A1

公开(公告)日：2017-06-08

申请号：US14989814

申请日：2016-01-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ke-Feng Lin ,  Hsuan-Po Liao ,  Ming-Shun Hsu ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shih-Teng Huang

IPC: H01L29/861 ,  H01L29/06

CPC classification number: H01L29/8615 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/8613

Abstract: A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region.

公开(公告)号：US09443958B2

公开(公告)日：2016-09-13

申请号：US14506700

申请日：2014-10-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66689 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7835

Abstract: A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric layer. The substrate has a first insulating structure disposed therein. The gate structure is disposed on the substrate and comprises a first portion covering a portion of the first insulating structure. The drain region and the source region are disposed in the substrate at two respective sides of the gate, and comprise a first conductivity type. The base region encompasses the source region, wherein the base region comprises a second conductivity type complementary to the first conductivity type. The gate dielectric layer is between the gate and the drain region, the base region and the substrate. The gate structure further comprises a second portion penetrating into the base region. A method of forming the HVMOS is further provided.

Abstract translation: 提供一种HVMOS晶体管器件。 HVMOS具有基板，栅极结构，漏极区域和源极区域，基极区域和栅极介电层。 基板具有设置在其中的第一绝缘结构。 栅极结构设置在衬底上并且包括覆盖第一绝缘结构的一部分的第一部分。 漏极区域和源极区域在栅极的两个相应侧设置在衬底中，并且包括第一导电类型。 基极区域包围源极区域，其中基极区域包括与第一导电类型互补的第二导电类型。 栅极电介质层位于栅极和漏极区域之间，基极区域和衬底之间。 栅极结构还包括穿入基底区域的第二部分。 还提供了形成HVMOS的方法。

公开(公告)号：US20160099340A1

公开(公告)日：2016-04-07

申请号：US14506700

申请日：2014-10-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66689 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7835

Abstract: A HVMOS transistor device is provided. The HVMOS has a substrate, a gate structure, a drain region and a source region, a base region and a gate dielectric layer. The substrate has a first insulating structure disposed therein. The gate structure is disposed on the substrate and comprises a first portion covering a portion of the first insulating structure. The drain region and the source region are disposed in the substrate at two respective sides of the gate, and comprise a first conductivity type. The base region encompasses the source region, wherein the base region comprises a second conductivity type complementary to the first conductivity type. The gate dielectric layer is between the gate and the drain region, the base region and the substrate. The gate structure further comprises a second portion penetrating into the base region. A method of forming the HVMOS is further provided.

Abstract translation: 提供一种HVMOS晶体管器件。 HVMOS具有基板，栅极结构，漏极区域和源极区域，基极区域和栅极介电层。 基板具有设置在其中的第一绝缘结构。 栅极结构设置在衬底上并且包括覆盖第一绝缘结构的一部分的第一部分。 漏极区域和源极区域在栅极的两个相应侧设置在衬底中，并且包括第一导电类型。 基极区域包围源极区域，其中基极区域包括与第一导电类型互补的第二导电类型。 栅极电介质层位于栅极和漏极区域之间，基极区域和衬底之间。 栅极结构还包括穿入基底区域的第二部分。 还提供了形成HVMOS的方法。

公开(公告)号：US09196717B2

公开(公告)日：2015-11-24

申请号：US13629609

申请日：2012-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/78 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/7816

Abstract: A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 提供HV MOS晶体管器件。 HV MOS晶体管器件包括至少包括形成在其上的绝缘区域的衬底，位于衬底上并覆盖绝缘区域的一部分的栅极，形成在衬底中的栅极的各个侧面处的漏极区域和源极区域， 以及形成在所述绝缘区域下方的第一注入区域。 衬底包括第一导电类型，漏极，源极和第一注入区域包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

公开(公告)号：US20150256146A1

公开(公告)日：2015-09-10

申请号：US14201914

申请日：2014-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu

IPC: H03H9/56 ,  H03H9/205

CPC classification number: H03H9/205 ,  H03H9/584 ,  H03H9/585 ,  H03H9/589

Abstract: A resonator filter includes a substrate, a bottom electrode formed on the substrate, a multi-layered coupling structure formed on the bottom electrode, a top electrode formed on the multi-layered coupling structure, a first piezoelectric layer sandwiched in between the bottom electrode and the multi-layered coupling structure, and a second piezoelectric layer sandwiched in between the multi-layered coupling structure and the top electrode. The multi-layered coupling structure includes at least an insulating material.

Abstract translation: 谐振器滤波器包括基板，形成在基板上的底部电极，形成在底部电极上的多层耦合结构，形成在多层耦合结构上的顶部电极，夹在底部电极和底部电极之间的第一压电层， 所述多层结合结构，以及夹在所述多层耦合结构和所述顶部电极之间的第二压电层。 多层结合结构至少包括绝缘材料。

公开(公告)号：US20140339636A1

公开(公告)日：2014-11-20

申请号：US13896289

申请日：2013-05-16

Applicant: United Microelectronics Corp.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0878

Abstract: A high voltage metal-oxide-semiconductor (HV MOS) transistor device includes a substrate, a drifting region formed in the substrate, a plurality of isolation structures formed in the drift region and spaced apart from each other by the drift region, a plurality of doped islands respectively formed in the isolation structures, a gate formed on the substrate, and a source region and a drain region formed in the substrate at respective two sides of the gate. The gate covers a portion of each isolation structure. The drift region, the source region, and the drain region include a first conductivity type, the doped islands include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 高压金属氧化物半导体（HV MOS）晶体管器件包括衬底，形成在衬底中的漂移区域，形成在漂移区域中并由漂移区域彼此分开的多个隔离结构，多个 分别形成在隔离结构中的掺杂岛，形成在衬底上的栅极，以及在栅极的相应两侧形成在衬底中的源极区和漏极区。 门覆盖每个隔离结构的一部分。 漂移区域，源区域和漏极区域包括第一导电类型，掺杂岛包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。

公开(公告)号：US20140091389A1

公开(公告)日：2014-04-03

申请号：US13629608

申请日：2012-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/78

CPC classification number: H01L29/0878 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7816

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 高电压金属氧化物半导体晶体管器件包括其中形成有绝缘区域的衬底，覆盖绝缘区域的一部分并形成在衬底上的栅极，形成在栅极各侧的源极区域和漏极区域 基板，形成在基板中并与栅极部分重叠的主体区域，以及形成在栅极下方并与主体区域相邻的基板中的第一注入区域。 衬底和体区包括第一导电类型。 源极区域，漏极区域和第一注入区域包括第二导电类型。 第一导电类型和第二导电类型彼此互补。

公开(公告)号：US09997643B2

公开(公告)日：2018-06-12

申请号：US14989814

申请日：2016-01-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ke-Feng Lin ,  Hsuan-Po Liao ,  Ming-Shun Hsu ,  Chih-Chung Wang ,  Chiu-Te Lee ,  Shih-Teng Huang

IPC: H01L29/02 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L29/8615 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/8613

Abstract: A diode structure includes a rectangular first doping region, and a second doping region surrounds the first doping region wherein the first doping region and the second doping region are separated by a first isolation structure. A third doping region surrounds the second doping region wherein the second doping region and the third doping region are separated by a second isolation structure. The first isolation structure, the second doping region, the second isolation structure and the third doping region are arranged in a quadruple concentric rectangular ring surrounding the first doping region.

公开(公告)号：US09825147B2

公开(公告)日：2017-11-21

申请号：US15231792

申请日：2016-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/66689 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7835

Abstract: A method of forming a HVMOS transistor device is provided. A substrate is provided. A first insulation structure and a trench are formed in the substrate. A base region having a second conductivity type is formed, wherein the base region completely encompasses the trench. Next, a gate dielectric layer and a gate structure are formed in the trench and covering a portion of the first insulation structure. Then, a drain region and a source region are formed in the substrate at two respective sides of the gate structure, and the drain region and the source region comprise a first conductivity type complementary to the second conductivity type. A channel is defined between the source region and the drain region along a first direction.

公开(公告)号：US20160351690A1

公开(公告)日：2016-12-01

申请号：US15231792

申请日：2016-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shun Hsu

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/66689 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7835

Abstract: A method of forming a HVMOS transistor device is provided. A substrate is provided. A first insulation structure and a trench are formed in the substrate. A base region having a second conductivity type is formed, wherein the base region completely encompasses the trench. Next, a gate dielectric layer and a gate structure are formed in the trench and covering a portion of the first insulation structure. Then, a drain region and a source region are formed in the substrate at two respective sides of the gate structure, and the drain region and the source region comprise a first conductivity type complementary to the second conductivity type. A channel is defined between the source region and the drain region along a first direction.

Abstract translation: 提供了一种形成HVMOS晶体管器件的方法。 提供基板。 在衬底中形成第一绝缘结构和沟槽。 形成具有第二导电类型的基极区域，其中基极区域完全包围沟槽。 接下来，在沟槽中形成栅极电介质层和栅极结构，并覆盖第一绝缘结构的一部分。 然后，在栅极结构的两个相应侧的衬底中形成漏极区域和源极区域，并且漏极区域和源极区域包括与第二导电类型互补的第一导电类型。 沿着第一方向在源极区域和漏极区域之间限定沟道。