公开(公告)号：US11742412B2

公开(公告)日：2023-08-29

申请号：US16985242

申请日：2020-08-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chun-Jen Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161

CPC classification number: H01L29/6656 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823821 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/1608 ,  H01L29/24 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

公开(公告)号：US10957762B2

公开(公告)日：2021-03-23

申请号：US16878542

申请日：2020-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Che-Hsien Lin ,  Cheng-Yeh Huang ,  Chun-Jen Huang ,  Yu-Chih Su ,  Yao-Jhan Wang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

公开(公告)号：US10777657B2

公开(公告)日：2020-09-15

申请号：US15710820

申请日：2017-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang ,  Chun-Jen Huang

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/28 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.

公开(公告)号：US20200127089A1

公开(公告)日：2020-04-23

申请号：US16194379

申请日：2018-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Che-Hsien Lin ,  Cheng-Yeh Huang ,  Chun-Jen Huang ,  Yu-Chih Su ,  Yao-Jhan Wang

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

公开(公告)号：US10217866B2

公开(公告)日：2019-02-26

申请号：US15696201

申请日：2017-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/82

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US20250072015A1

公开(公告)日：2025-02-27

申请号：US18370402

申请日：2023-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Kun-Szu Tseng ,  Sheng-Yuan Hsueh ,  Yao-Jhan Wang

IPC: H01L29/94 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region, forming a fin-shaped structure on the MOSCAP region, forming a shallow trench isolation (STI) around the substrate and the fin-shaped structure, performing a first etching process to remove part of the STI on the MOSCAP region, and then performing a second etching process to remove part of the STI on the non-MOSCAP region and the MOSCAP region.

公开(公告)号：US20240413017A1

公开(公告)日：2024-12-12

申请号：US18220839

申请日：2023-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Ya-Ting Hu ,  Wei-Che Chen ,  Chang-Yih Chen ,  Kun-Szu Tseng ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.

公开(公告)号：US10892365B2

公开(公告)日：2021-01-12

申请号：US16792120

申请日：2020-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yeh Huang ,  Te-Chang Hsu ,  Chun-Jen Huang ,  Che-Hsien Lin ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L29/10 ,  H01L29/161 ,  H01L29/51 ,  H01L29/49 ,  H01L21/768 ,  H01L21/324

Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.

公开(公告)号：US20200279917A1

公开(公告)日：2020-09-03

申请号：US16878542

申请日：2020-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  Che-Hsien Lin ,  Cheng-Yeh Huang ,  Chun-Jen Huang ,  Yu-Chih Su ,  Yao-Jhan Wang

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311 ,  H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.

公开(公告)号：US20190148550A1

公开(公告)日：2019-05-16

申请号：US16244076

申请日：2019-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.