公开(公告)号：US09395802B2

公开(公告)日：2016-07-19

申请号：US14285448

申请日：2014-05-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain ,  Stephan Gaskins

IPC: G06F1/32 ,  G06F12/12 ,  G06F12/08 ,  G06F11/10 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  G11C29/44

CPC classification number: G06F3/0631 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0866 ,  G06F12/12 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/601 ,  G06F2212/608 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C29/787 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract translation: 一种装置包括熔丝阵列和商店。 保险丝阵列用多个核心的压缩配置数据编程。 存储器耦合到多个核心，并且包括多个子存储器，每个子存储器对应于多个核心中的每一个，多个核心中的一个核心在上电/复位时访问半导体熔丝阵列以读取，以及 对压缩的配置数据进行解压缩，并且在多个子存储器中的多个核心的每个内存储一个或多个高速缓存存储器的多个解压配置数据集。 多个核心中的每一个具有睡眠逻辑。 睡眠逻辑被配置为随后访问多个子商店中的每一个的对应的一个，以检索并使用解压配置数据集来初始化电源门控事件之后的一个或多个高速缓存。

公开(公告)号：US08982655B1

公开(公告)日：2015-03-17

申请号：US13972794

申请日：2013-08-21

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/16 ,  G06F11/1008 ,  G11C29/802

Abstract: An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core.

Abstract translation: 可以预期用于存储和提供配置数据给微处理器的装置。 该设备具有设置在管芯上的核心和熔丝阵列，该熔丝阵列设置在管芯上并且耦合到核心，其中熔丝阵列包括用于核心的压缩配置数据编程的多个半导体熔丝，其中压缩的配置数据 通过对与核心对应的虚拟熔丝阵列内的数据进行压缩而产生，并且其中核心在上电/复位时对压缩的配置数据进行访问和解压缩，以用于初始化核心内的元件。

公开(公告)号：US20150058598A1

公开(公告)日：2015-02-26

申请号：US13972609

申请日：2013-08-21

Applicant: VIA Technologies, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G06F9/38 ,  G06F9/50

CPC classification number: G06F9/3885 ,  G06F9/5077 ,  G06F15/76 ,  G11C17/16

Abstract: An apparatus is contemplated for storing and providing configuration data to an integrated circuit device, the apparatus has a fuse array and a plurality of cores. The fuse array is disposed on a die. The fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the fuse array. The each of the plurality of cores includes array control, configured to access the first and second pluralities of fuses, and configured to process first states of the first plurality of semiconductor fuses and second states of the second plurality of semiconductor fuses according to contents of a configuration data register.

Abstract translation: 设想用于存储并向集成电路装置提供配置数据的装置，该装置具有熔丝阵列和多个芯。 保险丝阵列设置在管芯上。 熔丝阵列具有第一多个半导体熔丝和第二多个半导体熔丝。 多个芯设置在管芯上，其中多个芯中的每一个都耦合到熔丝阵列。 多个核心中的每一个包括阵列控制，被配置为访问第一和第二多个保险丝，并且被配置为根据第一和第二多个保险丝的内容来处理第一多个半导体熔丝的第一状态和第二多个半导体熔丝的第二状态 配置数据寄存器。

公开(公告)号：US20150055429A1

公开(公告)日：2015-02-26

申请号：US13972794

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G06F11/1008 ,  G11C29/802

Abstract: An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core.

Abstract translation: 可以预期用于存储和提供配置数据给微处理器的装置。 该设备具有设置在管芯上的核心和熔丝阵列，该熔丝阵列设置在管芯上并且耦合到核心，其中熔丝阵列包括用于核心的压缩配置数据编程的多个半导体熔丝，其中压缩的配置数据 通过对与核心对应的虚拟熔丝阵列内的数据进行压缩而产生，并且其中核心在上电/复位时对压缩的配置数据进行访问和解压缩，以用于初始化核心内的元件。

公开(公告)号：US20150055427A1

公开(公告)日：2015-02-26

申请号：US13972725

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G06F15/76 ,  G11C29/802 ,  H03M13/13 ,  H03M13/19

Abstract: An apparatus has a fuse array, a device programmer, and a plurality of cores. The fuse array is disposed on a die, where the fuse array comprises a plurality of semiconductor fuses. The device programmer is coupled to the fuse array and is configured to access the configuration data, to compress the configuration data to yield compressed configuration data, and to program the fuse array with the compressed configuration data. The plurality of cores is disposed separately on the die and is coupled to the fuse array, where each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

公开(公告)号：US20150055395A1

公开(公告)日：2015-02-26

申请号：US13972414

申请日：2013-08-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/16

CPC classification number: G11C17/16 ,  G06F15/7807 ,  G06F17/5054

Abstract: An apparatus includes a semiconductor fuse array, disposed on a die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is configured to store the configuration data in an encoded and compressed format. The second plurality of semiconductor fuses is configured to store first fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored.

公开(公告)号：US08879345B1

公开(公告)日：2014-11-04

申请号：US13972768

申请日：2013-08-21

Applicant: Via Technologies, Inc.

Inventor： G. Glenn Henry ,  Dinesh K. Jain

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/785 ,  G11C29/802

Abstract: An apparatus includes a semiconductor fuse array and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed configuration data. The array has a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores the configuration data in an encoded and compressed format. The second plurality of fuses stores first compressed fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the array and accesses all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores.

Abstract translation: 一种装置包括半导体熔丝阵列和多个芯。 半导体熔丝阵列设置在芯片上，其中是编程配置数据。 阵列具有第一多个保险丝和第二多个保险丝。 第一组多个保险丝以编码和压缩格式存储配置数据。 第二多个保险丝存储第一压缩熔丝校正数据，其指示与其先前存储的状态将改变其状态的第一多个保险丝内的第一个或多个保险丝对应的位置和值。 多个芯设置在管芯上，其中多个芯中的每个芯耦合到阵列，并且在加电/复位期间访问所有压缩的配置数据，以用于初始化多个芯内的元件。