公开(公告)号：US10379870B2

公开(公告)日：2019-08-13

申请号：US15644670

申请日：2017-07-07

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Alexander Fainkichen ,  Ye Li

IPC: G06F9/44 ,  G06F9/4401 ,  G06F3/06 ,  G06F12/1009 ,  G06F9/38 ,  G06F12/121 ,  G06F12/1027

Abstract: A method of initializing a secondary processor pursuant to a soft reboot of system software comprises storing code to be executed by the secondary processor in memory, building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space, fetching a first instruction of the code based on a first virtual address in the first address space and the first page tables, and executing the code beginning with the first instruction to switch from the first to the second page tables. The method further comprises, fetching a next instruction of the code using a second virtual address, which is identically mapped to a corresponding machine address, turning off a memory management unit of the secondary processor, and executing a waiting loop until a predetermined location in the physical memory changes in value.

公开(公告)号：US09952895B2

公开(公告)日：2018-04-24

申请号：US14876831

申请日：2015-10-07

Applicant: VMWARE, INC.

Inventor： Andrei Warkentin ,  Irfan Ulla Khan ,  Cyprien Laplace ,  Harvey Tuch ,  Alexander Fainkichen

IPC: G06F13/24 ,  G06F13/00 ,  G06F9/48 ,  G06F13/26

CPC classification number: G06F9/4818 ,  G06F13/26

Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes the steps of obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a regular interrupt, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector, and disabling interrupts in the processor. On the other hand, if the received interrupt is a PNMI, a PNMI interrupt handler is executed using the interrupt vector as an input thereto.

公开(公告)号：US20230325222A1

公开(公告)日：2023-10-12

申请号：US17715292

申请日：2022-04-07

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Sunil Kotian ,  Ye Li ,  Cyprien Laplace ,  Regis Duchesne ,  Alexander Fainkichen ,  Shruthi Hiriyuru

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45595

Abstract: Disclosed are various examples of lifecycle and recovery management for virtualized data processing unit (DPU) management operating systems. A DPU device executes a DPU management hypervisor that communicates with a management service over a network. The DPU management hypervisor virtualizes DPU hardware resources and passes control of the virtualized DPU hardware resources to a DPU management operating system (OS) virtual machine (VM). The DPU management hypervisor maintains control of a management network interface card (NIC) of the DPU device.

公开(公告)号：US20230237010A1

公开(公告)日：2023-07-27

申请号：US17580866

申请日：2022-01-21

Applicant: VMware, Inc.

Inventor： Regis Duchesne ,  Andrei Warkentin ,  Cyprien Laplace ,  Ye Li ,  Alexander Fainkichen ,  Shruthi Hiriyuru ,  Sunil Kotian

IPC: G06F15/78 ,  G06F9/30

CPC classification number: G06F15/7842 ,  G06F9/30123

Abstract: Disclosed are various examples of providing provide efficient waiting for detection of memory value updates for Advanced RISC Machines (ARM) architectures. An ARM processor component instructs a memory agent to perform a processing action, and executes a waiting function. The waiting function ensures that the processing action is completed by the memory agent. The waiting function performs an exclusive load at a memory location, and a wait for event (WFE) instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set. Once the event register is set, the waiting function completes and a second processing action is executed by the ARM processor component.

公开(公告)号：US20230236916A1

公开(公告)日：2023-07-27

申请号：US17582055

申请日：2022-01-24

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Sunil Kotian ,  Jared McNeill ,  Cyprien Laplace ,  Shruthi Hiriyuru

IPC: G06F11/07 ,  G06F11/22 ,  G06F11/24

CPC classification number: G06F11/0772 ,  G06F11/0778 ,  G06F11/0793 ,  G06F11/2284 ,  G06F11/24

Abstract: A combined data processing unit (DPU) and server solution with DPU operating system (OS) integration is described. A DPU OS is executed on a DPU or other computing device, where the DPU OS exercises secure calls provided by a DPU's trusted firmware component, that may be invoked by DPU OS components to abstract DPU vendor-specific and server vendor-specific integration details. An invocation of one of the secure calls made on the DPU to communicate with its associated server computing device is identified. In an instance in which the one of the secure calls is invoked, the secure call invoked is translated into a call or request specific to an architecture of the server computing device and the call is performed, which may include sending a signal to the server computing device in a format interpretable by the server computing device.

公开(公告)号：US20230122654A1

公开(公告)日：2023-04-20

申请号：US18069851

申请日：2022-12-21

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Alexander Fainkichen ,  Ye Li ,  Regis Duchesne ,  Cyprien Laplace ,  Shruthi Hiriyuru ,  Sunil Kotian

IPC: G06F12/06 ,  G06F9/455 ,  G06F13/16 ,  G06F13/42

Abstract: Techniques for enabling efficient guest OS access to PCIe configuration space are provided. In one set of embodiments, a hypervisor can reserve a single host physical memory page in the host physical memory of a host system and can populate the single host physical memory page with a value indicating non-presence of PCIe device functions. The hypervisor can then create, for each guest physical memory page in a guest physical memory of a virtual machine (VM) corresponding to a PCIe configuration space of an absent PCIe device function in the VM, a mapping in the hypervisor's second-level page tables that maps the guest physical memory page to the single host physical memory page.

公开(公告)号：US11579918B2

公开(公告)日：2023-02-14

申请号：US17476090

申请日：2021-09-15

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Ye Li ,  Alexander Fainkichen

IPC: G06F9/455 ,  G06F11/34 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/50 ,  G06F11/30 ,  G06F1/329 ,  G06F9/48

Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

公开(公告)号：US11513825B2

公开(公告)日：2022-11-29

申请号：US16671086

申请日：2019-10-31

Applicant: VMware, Inc.

Inventor： Ye Li ,  David Ott ,  Cyprien Laplace ,  Andrei Warkentin ,  Alexander Fainkichen

IPC: G06F9/54 ,  G06F9/455 ,  G06F9/30 ,  G06F13/42

Abstract: System and method for providing trusted execution environments uses a peripheral component interconnect (PCI) device of a computer system to receive and process commands to create and manage a trusted execution environment for a software process running in the computer system. The trusted execution environment created in the PCI device is then used to execute operations for the software process.

公开(公告)号：US11210222B2

公开(公告)日：2021-12-28

申请号：US15878062

申请日：2018-01-23

Applicant: VMware, Inc.

Inventor： Ye Li ,  Cyprien Laplace ,  Andrei Warkentin ,  Alexander Fainkichen ,  Regis Duchesne

IPC: G06F12/0815 ,  G06F12/0808

Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.

公开(公告)号：US11150933B2

公开(公告)日：2021-10-19

申请号：US16355497

申请日：2019-03-15

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Ye Li ,  Alexander Fainkichen

IPC: G06F9/455 ,  G06F11/34 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/50 ,  G06F11/30 ,  G06F1/329 ,  G06F9/48

Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.