公开(公告)号：US6033958A

公开(公告)日：2000-03-07

申请号：US108107

申请日：1998-06-30

Applicant: Jih-Wen Chou ,  Cheng-Han Huang

Inventor： Jih-Wen Chou ,  Cheng-Han Huang

IPC: H01L21/8234

CPC classification number: H01L21/823462

Abstract: A method of forming dual voltage MOS transistors includes first forming a mask layer, covering one of the at least two device regions and exposing another one of the two device regions. A gate oxide layer is then formed by thermal oxidation on the exposed device region. After removing the mask layer and exposing another gate oxide formed therebeneath, polysilicon gates for both of the two device regions can be formed.

Abstract translation: 形成双电压MOS晶体管的方法包括：首先形成掩模层，覆盖所述至少两个器件区域中的一个并暴露两个器件区域中的另一个。 然后通过在暴露的器件区域上的热氧化形成栅极氧化物层。 在去除掩模层并暴露另外形成的栅极氧化物之后，可以形成用于两个器件区域的多晶硅栅极。

公开(公告)号：US20120169386A1

公开(公告)日：2012-07-05

申请号：US13295270

申请日：2011-11-14

Applicant: Hsiao-Chung CHENG ,  Cheng-Han Huang ,  Meng-Sheng Chang

Inventor： Hsiao-Chung CHENG ,  Cheng-Han Huang ,  Meng-Sheng Chang

IPC: H03L7/00

CPC classification number: G11C19/28

Abstract: An exemplary resetting circuit adapted for regulating a voltage on an output terminal of a shift register is disclosed. The resetting circuit includes a reset driving module and a reset module. The reset driving module is received with an enable signal to output a control voltage signal to an output terminal of the reset driving module. The reset module is electrically coupled to the output terminal of the shift register and the output terminal of the reset circuit driving module, and is controlled by the control voltage signal on the output terminal of the reset driving module to determine whether switching on an electrical path between the output terminal of the shift register and a gate-off voltage level.

Abstract translation: 公开了一种适于调节移位寄存器的输出端上的电压的示例性复位电路。 复位电路包括复位驱动模块和复位模块。 复位驱动模块被接收有使能信号，以将控制电压信号输出到复位驱动模块的输出端子。 复位模块电耦合到移位寄存器的输出端和复位电路驱动模块的输出端，并由复位驱动模块的输出端上的控制电压信号控制，以确定是否接通电路 在移位寄存器的输出端子与栅极截止电压电平之间。

公开(公告)号：US20110212081A1

公开(公告)日：2011-09-01

申请号：US13107202

申请日：2011-05-13

Applicant: Sarwar Hashmi ,  Chuan Yang ,  Jun Zhang ,  Cheng-Han Huang

Inventor： Sarwar Hashmi ,  Chuan Yang ,  Jun Zhang ,  Cheng-Han Huang

IPC: A61K39/395 ,  C12N5/02 ,  C12N5/00 ,  A61K38/00 ,  A61K31/7088 ,  A61P3/00

CPC classification number: A61K38/1709 ,  C07K14/4702 ,  C12N15/113 ,  C12N2310/14

Abstract: Disclosed herein are methods and cell lines used in fat regulation. The methods and cell lines incorporate Krüppel-like factors including, without limitation, klf-1 and klf-3.

Abstract translation: 本文公开了用于脂肪调节的方法和细胞系。 方法和细胞系包含Krüppel样因子，包括但不限于klf-1和klf-3。

公开(公告)号：US5723293A

公开(公告)日：1998-03-03

申请号：US553888

申请日：1995-11-06

Applicant: Cheng-Han Huang

Inventor： Cheng-Han Huang

IPC: C12N15/09 ,  C12Q1/68 ,  C07H21/04 ,  C12N15/00 ,  G01N33/555

CPC classification number: C12Q1/6881 ,  C12Q1/683 ,  C12Q2600/156 ,  C12Q2600/172 ,  Y10S435/81

Abstract: The invention provides a diagnostic method of determining Rh genotypes by the identification of the molecular basis of Rh polymorphisms. Specifically, the invention provides a method for directly determining Dd and associated CcEe genotypes with great accuracy, overcoming problems associated with traditional serologic typing methods and leading to a direct discrimination of D/D, D/d, and d/d genetic status. The diagnostic method allows genotyping of fetuses to assess the risk of hemolytic diseases caused by Rh alloimmunization and genetic counseling and/or testing of couples to predict the outcome of pregnancies in relation to Rh incompatibilities. The method of the invention preferably employs amplification of Rh nucleic acid sequences, and employs differential cleavage of RhD-, RhCc- and/or RhEe-specific nucleic acid sequences by a restriction enzyme. Furthermore, diagnostic kits for the determination of Rh genotypes are provided.

Abstract translation: 本发明提供了通过鉴定Rh多态性的分子基础来确定Rh基因型的诊断方法。 具体地说，本发明提供了一种以高精度直接测定Dd和相关CcEe基因型的方法，克服了与传统血清学分型方法相关的问题，导致直接鉴别D / D，D / d和d / d基因状态。 诊断方法允许胎儿进行基因分型，以评估Rh同种异体免疫和遗传咨询和/或夫妇检测引起的溶血性疾病的风险，以预测与Rh不相容性相关的妊娠结局。 本发明的方法优选使用Rh核酸序列的扩增，并采用限制性酶对RhD-，RhCc-和/或RhEe-特异性核酸序列进行差异切割。 此外，提供了用于确定Rh基因型的诊断试剂盒。

公开(公告)号：US5115296A

公开(公告)日：1992-05-19

申请号：US640835

申请日：1991-01-14

Applicant: Chen-Chiu Hsue ,  Cheng-Han Huang

Inventor： Chen-Chiu Hsue ,  Cheng-Han Huang

IPC: H01L21/316 ,  H01L21/336 ,  H01L21/60 ,  H01L23/485 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31662 ,  H01L23/485 ,  H01L29/41775 ,  H01L29/66659 ,  H01L2924/0002 ,  Y10S438/981

Abstract: A method for manufacturing a self-aligned contact MOS field effect transistor integrated circuit has a substrate doped with a first conductivity. The substrate has field oxide regions separating the planned active transistor regions, and gate dielectric/gate electrode structures over the designated channel regions for the integrated circuit device. Opposite type conductivity ions are implanted into the doped silicon substrate to form the lightly doped portion of the source/drain regions for the transistor. Dielectric spacers are formed on the sidewalls of the dielectric/gate electrode structures. A block out mask is formed over the source/drain regions designated to have self-aligned contacts made thereto. Opposite type conductivity ions are implanted into the substrate to form heavily doped portions to complete the formation of the source/drain regions in those nondesignated self-aligned contact regions. The block out mask is removed. The structure is subjected to an oxidizing atmosphere to preferentially oxidize polysilicon gate regions and heavily doped source/drain regions (thicker silicon dioxide) is compared to the lightly doped source/drain regions (thinner silicon dioxide). Opposite type conductivity ions are implanted into the doped subtrate to form heavily doped portion and to complete the formation of the source/drain regions in those designated self-aligned contact regions. Chemical dip etching is used to remove thin oxide over the designated self-aligned contact source/drain regions while leaving the thicker oxide layer remaining over the nondesignated source/drain regions. The appropriate metallurgy is provided to the designated self-aligned regions to electrically connect MOS field effect transistors into a desired integrated circuit.

Abstract translation: 用于制造自对准接触MOS场效应晶体管集成电路的方法具有掺杂有第一导电性的衬底。 衬底具有将预定的有源晶体管区域和用于集成电路器件的指定沟道区域上的栅极电介质/栅电极结构分离的场氧化物区域。 将相对类型的电导率离子注入到掺杂硅衬底中以形成用于晶体管的源/漏区的轻掺杂部分。 电介质隔离物形成在电介质/栅电极结构的侧壁上。 在被指定为具有自对准触点的源极/漏极区域上形成阻挡掩模。 将相对类型的电导率离子注入到衬底中以形成重掺杂部分，以完成那些非指定的自对准接触区域中的源/漏区的形成。 封锁屏蔽被移除。 该结构经受氧化气氛以优先氧化多晶硅栅极区域，并将重掺杂的源极/漏极区域（较厚的二氧化硅）与轻掺杂的源极/漏极区域（较薄的二氧化硅）进行比较。 将相对类型的电导率离子注入到掺杂的子步骤中以形成重掺杂部分，并且在这些指定的自对准接触区域中完成源极/漏极区的形成。 使用化学浸渍蚀刻去除指定的自对准接触源极/漏极区上的薄氧化物，同时留下较厚的氧化物层保留在非指定的源极/漏极区域上。 将适当的冶金提供给指定的自对准区域以将MOS场效应晶体管电连接到期望的集成电路中。

公开(公告)号：US20100215660A1

公开(公告)日：2010-08-26

申请号：US12710910

申请日：2010-02-23

Applicant: Sarwar Hashmi ,  Chuan Yang ,  Jun Zhang ,  Cheng-Han Huang

Inventor： Sarwar Hashmi ,  Chuan Yang ,  Jun Zhang ,  Cheng-Han Huang

IPC: A61K39/395 ,  A61K31/7088 ,  A61K38/16 ,  A61K38/00 ,  C12N5/10

CPC classification number: A61K38/1709 ,  C07K14/4702 ,  C12N15/113 ,  C12N2310/14

Abstract: Disclosed herein are methods and cell lines used in fat regulation. The methods and cell lines incorporate Krüppel-like factors including, without limitation, klf-1 and klf-3.

Abstract translation: 本文公开了用于脂肪调节的方法和细胞系。 方法和细胞系包含Krüppel样因子，包括但不限于klf-1和klf-3。

公开(公告)号：US06037201A

公开(公告)日：2000-03-14

申请号：US040215

申请日：1998-03-17

Applicant: Meng-Jin Tsai ,  Cheng-Han Huang

Inventor： Meng-Jin Tsai ,  Cheng-Han Huang

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/28194 ,  Y10S148/163

Abstract: A method for manufacturing mixed-mode devices that can eliminate watermarks resulting from the formation of residues at the dead corner space of an inverted trapezium-shaped structure at the upper end of a shallow trench during dual gate-oxide processing operation. This method uses the same chemical processing conditions for etching the oxide layer and the removal of photoresist layer, so that no watermarks remain after the etching and cleaning processes. MOS transistors are formed over the thin gate oxide layer region and the thick gate oxide region are of, two types, each having a different gate oxide layer thickness so that each has a different operating voltage.

Abstract translation: 一种用于制造混合模式装置的方法，其可以消除在双栅极氧化物处理操作期间在浅沟槽的上端处的倒梯形结构的死角空间处形成残留物所产生的水印。 该方法使用相同的化学处理条件来蚀刻氧化物层和去除光致抗蚀剂层，使得在蚀刻和清洁工艺之后不会保留水印。 在薄栅极氧化物层区域上形成MOS晶体管，厚栅极氧化物区域分别具有不同的栅极氧化层厚度，每个具有不同的工作电压。

公开(公告)号：US5965464A

公开(公告)日：1999-10-12

申请号：US989757

申请日：1997-12-12

Applicant: Meng-Jin Tsai ,  Cheng-Han Huang ,  Te-Chuan Liao ,  Chen-Wei Lee

Inventor： Meng-Jin Tsai ,  Cheng-Han Huang ,  Te-Chuan Liao ,  Chen-Wei Lee

IPC: H01L21/8234 ,  H01L21/302

CPC classification number: H01L21/823468

Abstract: A method for forming a double spacer structure comprising the steps of first providing a semiconductor substrate that has a first gate and a second gate already formed thereon, wherein the gate length of the second gate is greater than the gate length of the first gate. Then, a first insulating layer is formed over the substrate and the gates. Next, a photoresist layer is formed over the first insulating layer above the second gate while exposing the first insulating layer above the first gate. Subsequently, a first etching operation is performed to establish a first spacer structure along the sidewalls of the first gate, and then the photoresist layer is removed leaving the first insulating layer over the second gate. Thereafter, a second insulating layer is formed over the substrate, the first gate and the first insulating layer, and then a second etching operation is performed to establish a second spacer structure along the sidewalls of the second gate. Therefore, a second spacer that has a width greater than the first spacer does is finally obtained.

Abstract translation: 一种形成双间隔结构的方法，包括以下步骤：首先提供半导体衬底，该半导体衬底具有已经形成在其上的第一栅极和第二栅极，其中第二栅极的栅极长度大于第一栅极的栅极长度。 然后，在衬底和栅极上形成第一绝缘层。 接下来，在第一栅极上方的第一绝缘层上方形成光致抗蚀剂层，同时使第一绝缘层暴露在第一栅极之上。 随后，执行第一蚀刻操作以沿着第一栅极的侧壁建立第一间隔结构，然后去除光致抗蚀剂层，离开第二绝缘层在第二栅极上。 此后，在衬底，第一栅极和第一绝缘层上形成第二绝缘层，然后进行第二蚀刻操作，以沿着第二栅极的侧壁建立第二间隔结构。 因此，最终获得具有大于第一间隔物的宽度的第二间隔物。