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公开(公告)号：US09704594B1
公开(公告)日：2017-07-11
申请号：US15047113
申请日：2016-02-18
CPC分类号： G11C16/3427 , G06F11/1044 , G06F11/1072 , G11C7/02 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/3418
摘要： The present disclosure relates to apparatus, systems, and methods that address the migration of least significant in memory cells due to inter-cell interference (ICI). The disclosed embodiments include a control unit that is configured to characterize the vulnerability of memory cells to ICI, and appropriately encode data stored in the vulnerable memory cells to address ICI. This encoding scheme, referred to as “stuck-at” encoding scheme, can be separate from the generic error correcting code encoding. The stuck-at encoding scheme can decrease the bit error rate of flash memory devices.
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公开(公告)号：US20220171992A1
公开(公告)日：2022-06-02
申请号：US17668037
申请日：2022-02-09
发明人： Wen Ma , Minghai Qin , Won Ho Choi , Pi-Feng Chiu , Martin Lueker-Boden
摘要： Exemplary methods and apparatus are disclosed that implement super-sparse image/video compression by storing image dictionary elements within a cross-bar resistive random access memory (ReRAM) array (or other suitable cross-bar NVM array). In illustrative examples, each column of the cross-bar ReRAM array stores the values for one dictionary element (such as one 4×4 dictionary element). Methods and apparatus are described for training (configuring) the cross-bar ReRAM array to generate and store the dictionary elements by sequentially applying patches from training images to the array using an unstructured Hebbian training procedure. Additionally, methods and apparatus are described for compressing an input image by applying patches from the input image to the ReRAM array to read out cross-bar column indices identifying the columns storing the various dictionary elements that best fit the image. This may be done in parallel using a set of ReRAM arrays.
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公开(公告)号：US20200257936A1
公开(公告)日：2020-08-13
申请号：US16275167
申请日：2019-02-13
发明人： Wen Ma , Minghai Qin , Won Ho Choi , Pi-Feng Chiu , Martin Lueker-Boden
摘要： Exemplary methods and apparatus are disclosed that implement super-sparse image/video compression by storing image dictionary elements within a cross-bar resistive random access memory (ReRAM) array (or other suitable cross-bar NVM array). In illustrative examples, each column of the cross-bar ReRAM array stores the values for one dictionary element (such as one 4×4 dictionary element). Methods and apparatus are described for training (configuring) the cross-bar ReRAM array to generate and store the dictionary elements by sequentially applying patches from training images to the array using an unstructured Hebbian training procedure. Additionally, methods and apparatus are described for compressing an input image by applying patches from the input image to the ReRAM array to read out cross-bar column indices identifying the columns storing the various dictionary elements that best fit the image. This may be done in parallel using a set of ReRAM arrays.
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14.发明授权公开(公告)号：US10691537B2
公开(公告)日：2020-06-23
申请号：US16158650
申请日：2018-10-12
发明人： Chao Sun , Minghai Qin , Dejan Vucinic
摘要： Techniques are presented for efficiently storing deep neural network (DNN) weights or similar type data sets in non-volatile memory. For data sets, such as DNN weights, where the elements are multi-bit values, bits of the same level of significance from the elements of the data set are formed into data streams. For example, the most significant bit from each of the data elements are formed into one data stream, the next most significant bit into a second data stream, and so on. The different bit streams are then encoded with differing strengths of error correction code (ECC), with streams corresponding to more significant bits encoded with stronger ECC code than streams corresponding to less significant bits, giving the more significant bits of the data set elements a higher level of protection.
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15.发明申请公开(公告)号：US20200117539A1
公开(公告)日：2020-04-16
申请号：US16158650
申请日：2018-10-12
发明人： Chao Sun , Minghai Qin , Dejan Vucinic
摘要： Techniques are presented for efficiently storing deep neural network (DNN) weights or similar type data sets in non-volatile memory. For data sets, such as DNN weights, where the elements are multi-bit values, bits of the same level of significance from the elements of the data set are formed into data streams. For example, the most significant bit from each of the data elements are formed into one data stream, the next most significant bit into a second data stream, and so on. The different bit streams are then encoded with differing strengths of error correction code (ECC), with streams corresponding to more significant bits encoded with stronger ECC code than streams corresponding to less significant bits, giving the more significant bits of the data set elements a higher level of protection.
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16.发明授权公开(公告)号：US10290346B2
公开(公告)日：2019-05-14
申请号：US15388737
申请日：2016-12-22
发明人： Zvonimir Z. Bandic , Minghai Qin , Seung-Hwan Song
摘要： Aspects of the disclosure provide a method and a data storage apparatus for storing fractional bits per cell with low-latency read per page. In various embodiments, the memory cells are configured to store a fractional number of bits per cell using a multi-page construction with reduced number of read per page as compared to a single page construction. The data storage apparatus store data in a plurality of non-volatile memory (NVM) cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits. The data storage apparatus reads a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L−1 program states.
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公开(公告)号：US20180129440A1
公开(公告)日：2018-05-10
申请号：US15347472
申请日：2016-11-09
发明人： Zvonimir Z. Bandic , Seung-Hwan Song , Chao Sun , Minghai Qin , Dejan Vucinic
IPC分类号： G06F3/06
CPC分类号： G06F3/0634 , G06F3/0604 , G06F3/0607 , G06F3/0667 , G06F3/0679 , G06F3/0688
摘要： In general, a controller may perform a self-virtualization technique. The storage device may include storage access comprising multiple cells, and a controller. The controller may determine a maximum amount of storage access for a virtual machine workload when each cell is configured in a first level mode having a maximum allowable number of bits per cell. The controller may configure each cell to be in a second level mode having a number of bits per cell less than the maximum. The controller may determine a total number of bits in use in each cell and compare this total to a threshold number of bits in use in each cell. Based on the comparison, the controller may reconfigure one or more cells to be in a third level mode having a number of bits per cell greater than the number for the second level mode.
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公开(公告)号：US09836350B2
公开(公告)日：2017-12-05
申请号：US14871096
申请日：2015-09-30
CPC分类号： G06F11/1068 , G06F11/1012 , G11C13/0064 , G11C13/0069 , G11C29/52 , G11C2029/0411 , H03M13/2906 , H03M13/353 , H03M13/616
摘要： Embodiments disclosed herein generally relate to an error correction method for non-volatile memory. The error correction method writes data to a first location from a block of user data stored in DRAM. The data written to the first location is verified and errors are identified. Upon determining the number of identified errors exceed a threshold, the block of user data is re-writing to a second location. The data written to the second location is verified and errors are identified. The data written to the first location and the data written to the second location are compared and all discrepancy bits are erased in the comparison. A joint parity check matrix is built with the data written to the first location and the data written to the second location. A code word matrix is built with the comparison. A resultant of the joint parity check matrix and the code word matrix is determined if it is invertible.
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公开(公告)号：US11741188B2
公开(公告)日：2023-08-29
申请号：US17370716
申请日：2021-07-08
发明人： Wen Ma , Pi-Feng Chiu , Minghai Qin , Won Ho Choi , Martin Lueker-Boden
CPC分类号： G06F17/16 , G06N3/08 , G11C13/0002 , H03M1/12 , H03M1/74
摘要： An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.
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公开(公告)号：US11231993B2
公开(公告)日：2022-01-25
申请号：US16205099
申请日：2018-11-29
发明人： Minghai Qin
摘要： Systems and methods for implementing data protection techniques with symbol-based variable node updates for binary low-density parity-check (LDPC) codes are described. A semiconductor memory (e.g., a NAND flash memory) may read a set of data from a set of memory cells, determine a set of data state probabilities for the set of data based on sensed threshold voltages for the set of memory cells, generate a valid codeword for the set of data using an iterative LDPC decoding with symbol-based variable node updates and the set of data state probabilities, and store the valid codeword within the semiconductor memory or transfer the valid codeword from the semiconductor memory. The iterative LDPC decoding may utilize a message passing algorithm in which outgoing messages from a plurality of multi-variable nodes are generated using incoming messages (e.g., log-likelihood ratios or L-values) from a plurality of check nodes.
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