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11.发明授权Upsampling filter having one-bit multipliers for multiple spread-data streams 有权具有用于多个扩展数据流的一位乘法器的上采样滤波器公开(公告)号：US06603804B1
公开(公告)日：2003-08-05
申请号：US09411152
申请日：1999-10-01
IPC分类号： H04B169
CPC分类号： H03H17/0223
摘要： A transmit portion of a WB-CDMA transceiver generates one or more spread data streams having values represented by a single bit, allowing for filtering of spread and combined data streams with a root raised cosine (RRC) filter employing single-bit multipliers. The RRC filter is a digital filter that i) employs multiplication of two values in which the length of at least one value is one bit; ii) is preferably implemented with muxs or a simple logic operator; and iii) may employ upsampling and modulation encoding of filter coefficients to reduce the coefficient length to, for example, one bit. The RRC filter may be an FIR filter having either one-bit or multi-bit coefficients, and apply RRC filtering to a spread user stream either before or after the spread user streams are combined. For some implementations, RRC filters are employed to filter each spread user stream prior to combining several processed user steams. For other implementations, the multi-bit valued data stream representing the combined user streams is upsampled to form an upsampled data stream of single-bit values, and RRC filtering is then applied to the upsampled data stream. Alternatively, implementations may use upsampled RRC filter coefficients that allow RRC filtering on the combined spread user streams represented as a sequence of multi-bit values.
摘要翻译： WB-CDMA收发器的发送部分产生具有由单个比特表示的值的一个或多个扩展数据流，允许使用单比特乘法器的根升余弦（RRC）滤波器对扩展和组合数据流进行滤波。 RRC滤波器是数字滤波器，其i）采用其中至少一个值的长度为1比特的两个值的乘法; ii）优选地用多路复用器或简单的逻辑运算符实现; 和iii）可以采用滤波器系数的上采样和调制编码来将系数长度减小到例如一位。 RRC滤波器可以是具有一比特或多比特系数的FIR滤波器，并且在扩展用户流合并之前或之后对扩展用户流应用RRC滤波。 对于一些实现方式，采用RRC滤波器来在组合若干已处理的用户流之前过滤每个扩展用户流。 对于其他实施方式，表示组合用户流的多位值数据流被上采样以形成单位值的上采样数据流，然后将RRC滤波应用于上采样数据流。 或者，实现可以使用上采样的RRC滤波器系数，其允许对表示为多位值序列的组合扩展用户流进行RRC过滤。
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公开(公告)号：US20190229415A1
公开(公告)日：2019-07-25
申请号：US16370987
申请日：2019-03-30
摘要： An apparatus includes a first integrated circuit (IC) that includes a first radio-frequency (RF) circuit to process RF signals, a first antenna port to couple to one or more antennas, and a first switch integrated in the first IC and coupled to the first antenna port. The apparatus further includes a second IC that includes a second RF circuit to process RF signals, a second antenna port to couple to the one or more antennas, and a second switch integrated in the second IC and coupled to the second antenna port.
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公开(公告)号：US09647623B2
公开(公告)日：2017-05-09
申请号：US12571092
申请日：2009-09-30
CPC分类号： H04B1/16 , H03G3/3068
摘要： A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.
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公开(公告)号：US08428536B2
公开(公告)日：2013-04-23
申请号：US12323040
申请日：2008-11-25
CPC分类号： H04B1/28 , H03G3/3068
摘要： A receiver (100) includes a first element (110) with a signal input, a control input, a signal output, and gain steps of a first magnitude, a signal processing circuit (120-168) with a signal input coupled to the first element, and a signal output, a second element (180) that has a signal input coupled to signal processing circuit, a control input, a signal output, and gain steps of a second magnitude smaller than the first magnitude, and a controller (180) that has a control output coupled to the first element (110), a control output coupled to the second element (180), and that adjusts receiver (100) gain by changing the first element (110) gain by a first magnitude, changing the second element (180) gain by substantially an inverse first magnitude, and subsequently changing the gain of the second element (180) by steps of the second magnitude to achieve a desired gain.
摘要翻译： 接收器（100）包括具有信号输入的第一元件（110），控制输入，信号输出和第一幅度的增益步长，信号处理电路（120-168），信号输入端与第一 元件和信号输出，具有耦合到信号处理电路的信号输入的第二元件（180），小于第一幅度的第二幅度的控制输入，信号输出和增益步骤，以及控制器（180） ），其具有耦合到所述第一元件（110）的控制输出，耦合到所述第二元件（180）的控制输出，并且通过将所述第一元件（110）增益改变第一量值来调整接收器（100）增益， 第二元件（180）通过基本上相反的第一幅度增益，随后通过第二幅度的步长来改变第二元件（180）的增益，以实现期望的增益。
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15.发明申请LOW NOISE AMPLIFIER (LNA) SUITABLE FOR USE IN DIFFERENT TRANSMISSION ENVIRONMENTS AND RECEIVER USING SUCH AN LNA 有权低噪声放大器（LNA）适用于不同传输环境和接收器使用此类别公开(公告)号：US20120220255A1
公开(公告)日：2012-08-30
申请号：US13036892
申请日：2011-02-28
IPC分类号： H04B1/16
CPC分类号： H04B1/16 , H03F3/193 , H03F3/45179 , H03F2200/294 , H03F2203/45301 , H03F2203/45302 , H03F2203/45306 , H03F2203/45318 , H03F2203/45621 , H03F2203/45704
摘要： A low-noise amplifier includes first and second transconductance paths and first and second variable capacitive dividers. The first transconductance path has a first terminal for receiving a first input signal, a control terminal, and a second terminal for providing a first output signal. The second transconductance path has a first terminal for receiving a second input signal, a control terminal, and a second terminal for providing a second output signal. The first variable capacitive divider has a first terminal for receiving the first input signal, a second terminal coupled to a reference voltage terminal, and an intermediate terminal coupled to the control terminal of the second transconductance path. The second variable capacitive divider has a first terminal for receiving the second input signal, a second terminal coupled to the reference voltage terminal, and an intermediate terminal coupled to the control terminal of the first transconductance path.
摘要翻译： 低噪声放大器包括第一和第二跨导路径以及第一和第二可变电容分压器。 第一跨导路径具有用于接收第一输入信号的第一端子，控制端子和用于提供第一输出信号的第二端子。 第二跨导路径具有用于接收第二输入信号的第一端子，控制端子和用于提供第二输出信号的第二端子。 第一可变电容分压器具有用于接收第一输入信号的第一端子，耦合到参考电压端子的第二端子和耦合到第二跨导路径的控制端子的中间端子。 第二可变电容分压器具有用于接收第二输入信号的第一端子，耦合到参考电压端子的第二端子和耦合到第一跨导路径的控制端子的中间端子。
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16.发明申请Signal Processor Suitable for Low Intermediate Frequency (LIF) or Zero Intermediate Frequency (ZIF) Operation 有权信号处理器适用于低中频（LIF）或零中频（ZIF）操作公开(公告)号：US20110076977A1
公开(公告)日：2011-03-31
申请号：US12571092
申请日：2009-09-30
IPC分类号： H04B1/06
CPC分类号： H04B1/16 , H03G3/3068
摘要： A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops.
摘要翻译： 一种用于射频（RF）接收机的信号处理器包括多个分布式信号处理元件，其中第一个接收输入信号，最后一个提供输出信号，并且多个增益元素散布在所述多个 的分布式信号处理元件。 信号处理器还包括耦合到所述多个增益元件中对应的增益元件的相应输出端的相同的多个峰值检测器，以及具有耦合到每个峰值检测器的输出的输入的自动增益控制器，以及耦合到多个 获得元素。 自动增益控制器独立地控制多个增益元件中的每一个以形成相同的多个独立的自动增益控制（AGC）回路。
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公开(公告)号：US07580481B2
公开(公告)日：2009-08-25
申请号：US10836775
申请日：2004-04-30
IPC分类号： H04L27/00
CPC分类号： H04L27/364
摘要： Timing correction is affected for mismatch between channels in an I/Q demodulator. The respective demodulated I-channel and Q-channel are correlated and integrated so generate a timing control signal that is applied to a variable delay element. The variable delay element inserts a variable time delay in an ADC clock signal that is applied to either the I-channel ADC or the Q-channel ADC.
摘要翻译： 定时校正受I / Q解调器通道之间不匹配的影响。 相应的解调的I信道和Q信道被相关和积分，从而产生应用于可变延迟元件的定时控制信号。 可变延迟元件在应用于I通道ADC或Q通道ADC的ADC时钟信号中插入可变时间延迟。
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18.发明授权公开(公告)号：US07167694B2
公开(公告)日：2007-01-23
申请号：US10412871
申请日：2003-04-14
IPC分类号： H04B7/08
CPC分类号： H04N5/4446 , H03D3/006 , H03D3/007 , H03L7/18 , H04H40/90 , H04N5/4401 , H04N5/50 , H04N7/20 , H04N21/4263
摘要： Multi-tuner receiver architectures and associated methods are disclosed that provide initial analog coarse tuning of desired channels within a received signal spectrum, such as transponder channels within a set-top box signal spectrum for satellite communications. These multi-tuner satellite receiver architectures provide significant advantages over prior direct down-conversion (DDC) architectures and low intermediate-frequency (IF) architectures, particularly where two tuners are desired on the same integrated circuit. Rather than using a low-IF frequency or directly converting the desired channel frequency to DC, initial coarse tuning provided by analog coarse tuning circuitry allows for a conversion to a frequency range around DC. This coarse tuning circuitry can be implemented, for example, using a large-step local oscillator (LO) that provides a coarse tune analog mixing signal. Once mixed down, the desired channel may then be fine-tuned through digital processing, such as through the use of a wide-band analog-to-digital converter (ADC) or a narrow-band tunable bandpass ADC.
摘要翻译： 公开了多调谐器接收机架构和相关方法，其提供在接收信号频谱内的期望信道的初始模拟粗调，例如用于卫星通信的机顶盒信号频谱内的应答器信道。 这些多调谐器卫星接收机架构提供了优于先前的直接下变频（DDC）架构和低中频（IF）架构的显着优点，特别是在同一集成电路上需要两个调谐器时。 不是使用低IF频率或直接将期望的信道频率转换为DC，而是由模拟粗调谐电路提供的初始粗调调可以转换到大约DC的频率范围。 该粗调谐电路可以例如使用提供粗调模拟混频信号的大步本地振荡器（LO）来实现。 一旦混合，则可以通过数字处理（例如通过使用宽带模数转换器（ADC）或窄带可调谐带通ADC）来微调所需的信道。
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公开(公告)号：US06313769B1
公开(公告)日：2001-11-06
申请号：US09563874
申请日：2000-05-03
IPC分类号： H03M106
CPC分类号： H03M1/1019 , H03M1/66
摘要： A signal processing system includes a main digital-to-analog converter (DAC) for receiving a digital baseband signal and converting the digital signal into an analog signal. Also included in the system is a connection circuit for receiving the analog signal, and output terminal, and an analog filter coupled between the connection circuit and the output terminal for filtering the analog signal. The system includes a calibration circuit coupled between the connection circuit and the output terminal for setting an offset voltage level. The calibration circuit includes (a) an approximation circuit coupled to the output terminal and operable during a calibration mode to determine the offset voltage level and store the offset voltage level as a digital offset signal and (b) an offset DAC coupled between the connection circuit and the approximation circuit for converting the digital offset signal into the offset voltage level. The connection circuit, which is a node, subtracts the offset voltage level from the analog signal.
摘要翻译： 信号处理系统包括用于接收数字基带信号并将数字信号转换为模拟信号的主数/模转换器（DAC）。 该系统还包括用于接收模拟信号的连接电路和输出端子，以及耦合在连接电路和输出端子之间的模拟滤波器，用于对模拟信号进行滤波。 该系统包括耦合在连接电路和输出端子之间的校准电路，用于设定偏移电压电平。 校准电路包括（a）耦合到输出端并且可在校准模式期间操作以确定偏移电压电平并将偏移电压电平存储为数字偏移信号的近似电路，以及（b）耦合在连接电路 以及用于将数字偏移信号转换为偏移电压电平的近似电路。 作为节点的连接电路从模拟信号中减去偏移电压电平。
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20.发明授权公开(公告)号：US06181212B2
公开(公告)日：2001-01-30
申请号：US09238990
申请日：1999-01-28
IPC分类号： H03L7197
CPC分类号： H03C3/0933 , H03C3/40 , H03D7/163 , H03D7/165 , H03L7/1976 , H04B1/00 , H04B1/28 , H04B1/406
摘要： A method and apparatus for generating two disparate frequency reference signals using a single phase locked loop. The circuit includes a local oscillator for generating a reference signal and a phase comparator for comparing the reference signal with a feedback signal. The output of the phase comparator is converted to a first one of the desired output frequencies by a voltage controlled oscillator. That signal is also fed to a variable frequency divider circuit under control of a &Sgr;/&Dgr; converter which generates a lower frequency signal without creating a secondary frequency tone. The lower frequency signal is the second of the output frequencies. This signal also is fed back to the second input of the phase comparator through a fixed frequency divider.
摘要翻译： 一种用于使用单个锁相环产生两个不同频率参考信号的方法和装置。 电路包括用于产生参考信号的本地振荡器和用于将参考信号与反馈信号进行比较的相位比较器。 相位比较器的输出通过压控振荡器转换成所需输出频率的第一个。 该信号也在SIGMA / DELTA转换器的控制下馈送到可变分频器电路，该转换器产生较低频率信号而不产生辅助频率音调。 低频信号是输出频率的第二个。 该信号也通过固定分频器反馈到相位比较器的第二输入端。
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