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公开(公告)号：US5644688A
公开(公告)日：1997-07-01
申请号：US398410
申请日：1995-03-02
CPC分类号： G06T17/20
摘要： A method for simulating changes to the topography of a workpiece, e.g. a semiconductor wafer, as it undergoes process steps. The method may be used to simulated isotropic or anisotropic deposition or etch process steps. A solids modeling system is used to define and deform material solids. Material solids represent the different materials on a workpiece. A plurality of trajectory solids are constructed to cause the deformation of the material solids. Deformation of a material solid is accomplished through the performance of boolean operations between the material solid and one or more trajectory solids. A characteristic of a trajectory solid, e.g. a radius or height, relates to the rate of etch or deposition for the particular process step. The method of construction of trajectory solids in the present invention enables simulation of spatially varying process steps, avoids the creation of invalid self-intersecting surfaces and minimizes the creation of small edges that lead to irregular surfaces.
摘要翻译： 用于模拟工件的形貌变化的方法，例如， 半导体晶片，因为它经历了工艺步骤。 该方法可用于模拟各向同性或各向异性沉积或蚀刻工艺步骤。 固体建模系统用于定义和变形材料固体。 材料固体表示工件上的不同材料。 多个轨迹固体被构造成引起材料固体的变形。 通过在材料固体和一个或多个轨迹固体之间执行布尔运算来实现材料固体的变形。 轨迹固体的特征，例如。 半径或高度涉及特定工艺步骤的蚀刻或沉积速率。 在本发明中构造轨迹固体的方法能够模拟空间变化的工艺步骤，避免产生无效的自相交表面并且最小化导致不规则表面的小边缘的产生。
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公开(公告)号：US5282140A
公开(公告)日：1994-01-25
申请号：US904001
申请日：1992-06-24
申请人： Satoshi Tazawa , Tetsuya Abe , Francisco A. Leon
发明人： Satoshi Tazawa , Tetsuya Abe , Francisco A. Leon
CPC分类号： G06F17/5018 , G06F2217/16
摘要： In a three-dimensional (3-D) topography simulator, a method for removing sources of particle flux because of neighboring topology, for a point on a workpiece undergoing a deposition or etch process step. The method is practiced in a Generalized Solids Modeling system that utilizes a boundary representation model for representing a workpiece as one or more material object solids. For any given point on the 3-D structure, the neighboring topography forms a complex shadowing mask with respect to sources of particle flux, thus making analytical determination of visible sources of incoming particle flux difficult. The method is comprised generally of the steps of: defining a numerical mesh in a space over a surface of the workpiece; specifying an intensity of incident flux for each mesh point, identifying a set of mesh points defining a visible range of mesh points with respect to a particular target point and identifying mesh points in said set of mesh points that are obscured by neighboring topology.
摘要翻译： 在三维（3-D）地形模拟器中，由于相邻的拓扑结构，用于去除经历沉积或蚀刻工艺步骤的工件上的点的方法。 该方法在通用固体建模系统中实施，其利用用于将工件表示为一个或多个材料对象固体的边界表示模型。 对于3-D结构上的任何给定点，相邻的形貌相对于粒子通量来源形成复杂的阴影掩模，从而使进入的颗粒通量的可见光源的分析测定困难。 该方法通常包括以下步骤：在工件的表面上的空间中定义数字网格; 指定每个网格点的入射通量的强度，识别一组网格点，其定义相对于特定目标点的网格点的可见范围，并识别所述网格点集合中被相邻拓扑遮蔽的网格点。
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公开(公告)号：US07151881B2
公开(公告)日：2006-12-19
申请号：US10856127
申请日：2004-05-28
IPC分类号： G02B6/10
CPC分类号： G02B6/42 , G02B6/136 , G02B2006/12123 , H01L31/02327 , H01L31/0312 , H01L31/09 , H01L31/105 , H01L31/1105 , H01L31/1812 , Y02E10/50
摘要： An optical circuit including a semiconductor substrate; an optical waveguide formed in or on the substrate; and an optical detector formed in or on the semiconductor substrate, wherein the optical detector is aligned with the optical waveguide so as to receive an optical signal from the optical waveguide during operation, and wherein the optical detector has: a first electrode; a second electrode; and an intermediate layer between the first and second electrodes, the intermediate layer being made of a semiconductor material characterized by a conduction band, a valence band, and deep level energy states introduced between the conduction and valence bands.
摘要翻译： 一种包括半导体衬底的光学电路; 形成在基板中或基板上的光波导; 以及形成在所述半导体衬底中或之上的光学检测器，其中所述光学检测器与所述光波导对准，以便在操作期间从所述光波导接收光信号，并且其中所述光学检测器具有：第一电极; 第二电极; 以及在所述第一和第二电极之间的中间层，所述中间层由导电带和导带之间引入的导带，价带和深能级状态的半导体材料制成。
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公开(公告)号：US07075165B2
公开(公告)日：2006-07-11
申请号：US10856750
申请日：2004-05-28
IPC分类号： H01L31/075
CPC分类号： G02B6/12004 , G02B2006/12061 , H01L31/0232 , H01L31/0288 , H01L31/105 , H01L31/1812 , Y02E10/50
摘要： A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
摘要翻译： 一种制造检测器的方法，包括：在衬底中形成沟槽，所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中，所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层，第二层和第三层的部分，以产生上部基本平坦的表面，并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。
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公开(公告)号：US07001788B2
公开(公告)日：2006-02-21
申请号：US10858524
申请日：2004-05-28
IPC分类号： H01L21/00
CPC分类号： G02B6/12004 , G02B6/122 , G02B6/132 , G02B6/136 , G02B2006/121 , G02B2006/12104
摘要： A method of fabricating a waveguide mirror that involves etching a trench in a silicon substrate; depositing a film (e.g. silicon dioxide) over the surface of the silicon substrate and into the trench; ion etching the film to remove at least some of the deposited silicon dioxide and to leave a facet of film in inside corners of the trench; depositing a layer of SiGe over the substrate to fill up the trench; and planarizing the deposited SiGe to remove the SiGe from above the level of the trench.
摘要翻译： 一种制造波导反射镜的方法，涉及蚀刻硅衬底中的沟槽; 在硅衬底的表面上沉积膜（例如二氧化硅）并进入沟槽; 离子蚀刻膜以去除沉积的二氧化硅中的至少一些并且在沟槽的内部角落留下膜的小面; 在衬底上沉积一层SiGe以填充沟槽; 并且平坦化沉积的SiGe以从沟槽的高度上方除去SiGe。
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16.发明授权Method for accurate calculation of vertex movement for three-dimensional topography simulation 失效用于三维地形模拟的顶点运动的精确计算方法
公开(公告)号：US5377118A
公开(公告)日：1994-12-27
申请号：US252062
申请日：1994-06-01
CPC分类号： G06T17/20 , G06F17/5018 , G06F2217/74
摘要： A method for accurately calculating the movement of a vertex in a three-dimensional (3-D) topography simulator. The method is particularly suited for calculating vertex movement for cases in which etch/deposition rate depends on the angle between the surface normal and the vertical direction. A workpiece is represented as a collection of material solids. Each of the material solids has a boundary model representation. The method of the present invention is comprised primarily of the steps of: advancing edges and surface planes adjacent to the vertex, creating a set of 2-D solutions by clipping with pairs of adjacent surface planes; creating a set of combined 2-D solutions by clipping invalid sections of combined 2-D solutions; construct an arbitrary vertical plane that intersects the surface at the vertex point; constructing vertex trajectories for the vertex to be moved; and clipping constructed vertex trajectories at intersections of created surface and the constructed vertical plane.
摘要翻译： 一种精确计算三维（3-D）地形模拟器中顶点移动的方法。 该方法特别适合于在蚀刻/沉积速率取决于表面法线和垂直方向之间的角度的情况下计算顶点移动。 工件被表示为材料固体的集合。 每个材料实体都具有边界模型表示。 本发明的方法主要包括以下步骤：使靠近顶点的边缘和表面平行前进，通过相邻的表面平面对剪切形成一组二维解; 通过剪切合并的2-D解决方案的无效部分创建一组组合的二维解决方案; 构造在顶点与表面相交的任意垂直平面; 构造要移动的顶点的顶点轨迹; 并在创建的表面和构造的垂直平面的交点处剪切构造的顶点轨迹。
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公开(公告)号：US07205624B2
公开(公告)日：2007-04-17
申请号：US10959897
申请日：2004-10-06
IPC分类号： H01L31/00
CPC分类号： H01L31/035254 , B82Y20/00 , G02B6/12004
摘要： A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.
摘要翻译： 一种制造检测器的方法，所述方法包括在衬底上形成检测器芯材料岛，所述岛具有水平取向的顶端，垂直取向的第一侧壁和与所述第一侧壁相对的垂直取向的第二侧壁; 将第一掺杂剂注入到所述第一侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第一导电区域; 将第二掺杂剂注入所述第二侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第二导电区域; 制造到第一导电区域的顶端的第一电连接; 以及制造到所述第二导电区域的顶端的第二电连接。
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公开(公告)号：US07101725B2
公开(公告)日：2006-09-05
申请号：US10896754
申请日：2004-07-22
申请人： Yuichi Wada , Francisco A. Leon
发明人： Yuichi Wada , Francisco A. Leon
IPC分类号： H01L21/00
CPC分类号： G02B6/12004 , B82Y20/00 , C30B29/12 , C30B33/00 , G02B6/12 , G02B6/4214 , G02B6/43 , H01L21/84 , H01L27/1203 , H01L31/035254
摘要： A method of fabricating on optical detector, the method including providing a substrate that includes an optical waveguide formed therein and having a surface for fabricating microelectronic circuitry thereon; fabricating microelectronic circuitry on the substrate, the fabricating involving a plurality of sequential process phases; after a selected one of the plurality of sequential process phases has occurred and before the next process phase after the selected one of the plurality of process phases begins, fabricating an optical detector within the optical waveguide; and after fabricating the optical detector in the waveguide, completing the plurality of sequential process phases for fabricating the microelectronic circuitry.
摘要翻译： 一种在光学检测器上制造的方法，所述方法包括提供包括其中形成的光波导并且具有用于在其上制造微电子电路的表面的衬底; 在衬底上制造微电子电路，该制造涉及多个连续的工艺阶段; 在所述多个顺序处理阶段中的所选择的一个已经发生并且在所述多个处理阶段中所选择的一个处理阶段开始之后的下一个处理阶段之前，在所述光波导内制造光学检测器; 并且在波导中制造光学检测器之后，完成用于制造微电子电路的多个顺序处理阶段。
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19.发明授权Method of fabrication to sharpen corners of Y-branches in integrated optical components and other micro-devices 失效用于锐化集成光学部件和其他微器件中的Y分支的角部的制造方法公开(公告)号：US06818559B2
公开(公告)日：2004-11-16
申请号：US09814424
申请日：2001-03-21
申请人： Francisco A. Leon , Everett X. Wang
发明人： Francisco A. Leon , Everett X. Wang
IPC分类号： H01L21311
CPC分类号： G02B6/136 , G02B6/125 , G02B2006/1213
摘要： Substantially sharp corners for optical waveguides in integrated optical devices, photonic crystal devices, or for micro-devices, can be fabricated. Non-sharp corners such as rounded corners, are first formed using lithographic patterning and vertical etching. Next, isotropic etching is used to sharpen the rounded corners. A monitor can be used to determine if the rounded corners have been sufficiently sharpened by the isotropic etching.
摘要翻译： 可以制造用于集成光学器件，光子晶体器件或微器件中的光波导的基本上尖锐的角。 首先使用平版印刷图案和垂直蚀刻来形成诸如圆角的非锐角。 接下来，使用各向同性蚀刻来锐化圆角。 可以使用监视器来确定通过各向同性蚀刻圆角是否已被充分锐化。
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20.发明授权Method for modifying a chip layout to minimize within-die CD variations caused by flare variations in EUV lithography 失效用于修改芯片布局以最小化由EUV光刻中的光斑变化引起的管芯内CD变化的方法公开(公告)号：US06625802B2
公开(公告)日：2003-09-23
申请号：US10061615
申请日：2002-02-01
IPC分类号： G06F1750
CPC分类号： B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/36 , G03F1/70 , G03F7/70433 , G03F7/705 , G03F7/70941
摘要： A method including determining a first flare convolution based on a feature density of projected structures on a substrate layout, determining a second flare convolution based on a mask for a given substrate layout, determining a system flare variation by summing the first flare convolution and the second flare convolution, and determining a critical dimension variation based on the system flare variation.
摘要翻译： 一种方法，包括基于衬底布局上的投影结构的特征密度确定第一耀斑卷积，基于用于给定衬底布局的掩模确定第二耀斑卷积，通过将第一耀斑卷积和第二扩张卷积相加来确定系统闪光变化 闪耀卷积，并且基于系统耀斑变化确定临界尺寸变化。
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