公开(公告)号：US20240347665A1

公开(公告)日：2024-10-17

申请号：US18753975

申请日：2024-06-25

Applicant: Ciena Corporation

Inventor： Alireza Samani ,  Michael Vitic ,  Sean Sebastian O’Keefe

IPC: H01L31/107 ,  H01L31/0352 ,  H01L31/18 ,  H04B10/61

CPC classification number: H01L31/1075 ,  H01L31/035254 ,  H01L31/1812 ,  H04B10/616

Abstract: An avalanche photodiode includes a silicon layer on a substrate; a germanium layer on the silicon layer; and a plurality of contacts including a cathode, an anode, and at least two separate gain tuning contacts configured to adjust an electric field to tune multiplication of carriers. The at least two separate gain tuning contacts are configured to control the electric field in the germanium layer and silicon layer. The at least two separate gain tuning contacts are configured to tailor the electric field such that the multiplication of carriers is greater in the silicon layer than the germanium layer. This added gain tuning control can be used to tailor the electric field profile such that multiplication happens mostly in silicon to achieve lower excess noise and little to no bandwidth variation.

公开(公告)号：US20190189817A1

公开(公告)日：2019-06-20

申请号：US15843044

申请日：2017-12-15

Applicant: ATOMERA INCORPORATED

Inventor： Yi-Ann CHEN ,  Abid Husain ,  Hideki Takeuchi

IPC: H01L31/0352 ,  H01L27/146 ,  H01L31/18 ,  H01L31/109

CPC classification number: H01L31/035254 ,  H01L27/1461 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14645 ,  H01L27/14647 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/14692 ,  H01L31/109 ,  H01L31/1804

Abstract: A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

公开(公告)号：US20180301584A1

公开(公告)日：2018-10-18

申请号：US15936157

申请日：2018-03-26

Applicant: Quantum Semiconductor LLC

Inventor： Carlos Jorge R.P. Augusto

IPC: H01L31/109 ,  H01L29/06 ,  H01L31/105 ,  H01L31/0352 ,  H01L29/15 ,  H01L31/11 ,  H01L27/146 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/165 ,  H01S5/34

CPC classification number: H01L31/109 ,  H01L27/14601 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14681 ,  H01L29/0603 ,  H01L29/0653 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/155 ,  H01L29/165 ,  H01L29/66977 ,  H01L29/7371 ,  H01L31/035254 ,  H01L31/105 ,  H01L31/1105 ,  H01S5/3427

Abstract: An electrical device includes a counterdoped heterojunction selected from a group consisting of a pn junction or a p-i-n junction. The counterdoped junction includes a first semiconductor doped with one or more n-type primary dopant species and a second semiconductor doped with one or more p-type primary dopant species. The device also includes a first counterdoped component selected from a group consisting of the first semiconductor and the second semiconductor. The first counterdoped component is counterdoped with one or more counterdopant species that have a polarity opposite to the polarity of the primary dopant included in the first counterdoped component. Additionally, a level of the n-type primary dopant, p-type primary dopant, and the one or more counterdopant is selected to the counterdoped heterojunction provides amplification by a phonon assisted mechanism and the amplification has an onset voltage less than 1 V.

公开(公告)号：US09741889B2

公开(公告)日：2017-08-22

申请号：US14730502

申请日：2015-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bahman Hekmatshoar-Tabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L31/036 ,  H01L31/0747 ,  H01L31/0352 ,  B82Y20/00 ,  H01L31/0224 ,  H01L31/05

CPC classification number: H01L31/0747 ,  B82Y20/00 ,  H01L31/022441 ,  H01L31/035236 ,  H01L31/035254 ,  H01L31/0516 ,  Y02E10/50

Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.

公开(公告)号：US20170179316A1

公开(公告)日：2017-06-22

申请号：US14978469

申请日：2015-12-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L31/0352 ,  H01L31/18 ,  H01L31/20 ,  H01L31/0747

CPC classification number: H01L31/1804 ,  H01L31/028 ,  H01L31/035254 ,  H01L31/036 ,  H01L31/0745 ,  H01L31/0747 ,  Y02E10/547 ,  Y02P70/521

Abstract: A photovoltaic device includes a digital alloy buffer layer including a plurality of alternating layers of semiconductor material. An absorption layer epitaxially is grown on the digital alloy buffer layer, an intrinsic layer is formed on the absorption layer and a doped layer is formed on the intrinsic layer. A conductive contact is formed on the doped layer.

公开(公告)号：US09373938B2

公开(公告)日：2016-06-21

申请号：US14705188

申请日：2015-05-06

Applicant: SiFotonics Technologies Co., Ltd.

Inventor： Mengyuan Huang ,  Pengfei Cai ,  Liangbo Wang ,  Su Li ,  Wang Chen ,  Ching-yin Hong ,  Dong Pan

IPC: H01S5/00 ,  H01S5/20 ,  H01S5/02 ,  H01S5/30 ,  H01L31/0352 ,  H01L31/105 ,  H01S5/183 ,  H01S5/22

CPC classification number: H01S5/2054 ,  H01L31/035254 ,  H01L31/105 ,  H01S5/021 ,  H01S5/18325 ,  H01S5/18341 ,  H01S5/20 ,  H01S5/2004 ,  H01S5/2018 ,  H01S5/2059 ,  H01S5/2205 ,  H01S5/3013 ,  H01S5/3027 ,  H01S5/3031

Abstract: Various embodiments of a photonic device and fabrication method thereof are described herein. A device may include a substrate, a bottom contact layer, a current confinement layer, an intrinsic layer, an absorption layer, and a top contact layer. The bottom contact layer may be of a first polarity and may be disposed on the substrate. The current confinement layer may be disposed on the bottom contact layer. The intrinsic layer may be disposed on the current confinement layer. The absorption layer may be disposed on the intrinsic layer. The top contact layer may be of a second polarity and may be disposed on the absorption layer. The second polarity is opposite to the first polarity.

Abstract translation: 本文描述了光子器件的各种实施例及其制造方法。 器件可以包括衬底，底部接触层，电流限制层，本征层，吸收层和顶部接触层。 底部接触层可以是第一极性并且可以设置在基底上。 电流限制层可以设置在底部接触层上。 本征层可以设置在电流限制层上。 吸收层可以设置在本征层上。 顶部接触层可以是第二极性并且可以设置在吸收层上。 第二极性与第一极性相反。

公开(公告)号：US09246033B2

公开(公告)日：2016-01-26

申请号：US13604198

申请日：2012-09-05

Applicant: Bahman Hekmatshoar-Tabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

Inventor： Bahman Hekmatshoar-Tabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L31/028 ,  H01L31/0352 ,  H01L31/0747 ,  B82Y20/00

CPC classification number: H01L31/0747 ,  B82Y20/00 ,  H01L31/022441 ,  H01L31/035236 ,  H01L31/035254 ,  H01L31/0516 ,  Y02E10/50

Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.

Abstract translation: 光电器件和方法包括耦合到衬底的第一侧上的发射极侧结构的衬底和与衬底的第一侧相对的一侧的背侧结构。 发射极侧结构或背面结构包括在宽带隙层和窄带隙层之间交替的层，以提供与衬底有效增加的带偏移和/或在单个材料接触上有效地更高的掺杂水平的多层接触。 发射极触点耦合到器件的光收集端部上的发射极侧结构。 背面接触件与与光收集端部相对的背面结构耦合。

公开(公告)号：US20110051217A1

公开(公告)日：2011-03-03

申请号：US12942063

申请日：2010-11-09

Applicant: Peter G. Goetz ,  William S. Rabinovich

Inventor： Peter G. Goetz ,  William S. Rabinovich

IPC: G02F1/017 ,  G02F1/015 ,  H01L31/0352

CPC classification number: G02F1/015 ,  B82Y20/00 ,  G02F2201/122 ,  G02F2203/02 ,  G02F2203/12 ,  H01L31/022408 ,  H01L31/035254 ,  H01L31/105

Abstract: An electro-optic device with a doped semiconductor base and a plurality of pixels on the semiconductor base. Pixels include oppositely doped semiconductor layer and a top electrode formed on the oppositely doped semiconductor layer. The top electrode has a grid pattern with at least one busbar and a plurality of fingers extending from the busbar, and spacing between the fingers decreases with distance from the bondpad along the busbar. Each pixel can also include a multiple quantum well formed on the semiconductor base. The top electrode shape produces an approximately uniform lateral resistance in the pixel. An embodiment is a large area modulator for modulating retro-reflector systems, which typically use large area surface-normal modulators with large lateral current flow. Uniform resistance to each part of the modulator decreases location dependence of frequency response. A chirped grid electrode balances semiconductor sheet resistance and metal line resistance components of the series resistance.

Abstract translation: 一种具有掺杂半导体基底和半导体基底上的多个像素的电光器件。 像素包括相对掺杂的半导体层和形成在相对掺杂的半导体层上的顶部电极。 顶部电极具有至少一个母线和从母线延伸的多个指状物的栅格图案，并且指状物之间的间隔随着沿着母线的接合板的距离而减小。 每个像素还可以包括在半导体基底上形成的多量子阱。 顶部电极形状在像素中产生大致均匀的横向电阻。 一个实施例是用于调制后向反射器系统的大面积调制器，其通常使用具有大横向电流流动的大面积表面正常调制器。 对调制器各部分的均匀电阻降低了频率响应的位置依赖性。 啁啾的栅电极平衡了串联电阻的半导体薄层电阻和金属线电阻分量。

公开(公告)号：US07893348B2

公开(公告)日：2011-02-22

申请号：US11509886

申请日：2006-08-25

Applicant: Bastiaan Arie Korevaar ,  Loucas Tsakalakos

Inventor： Bastiaan Arie Korevaar ,  Loucas Tsakalakos

IPC: H01L31/00

CPC classification number: H01L31/035254 ,  B82Y20/00 ,  H01L31/035245 ,  H01L31/03529 ,  H01L31/075 ,  Y02E10/548 ,  Y10S977/712 ,  Y10S977/72 ,  Y10S977/762 ,  Y10S977/948 ,  Y10S977/954

Abstract: In some embodiments, the present invention is directed to photovoltaic (PV) devices comprising silicon (Si) nanowires as active PV elements, wherein such devices are typically thin film Si solar cells. Generally, such solar cells are of the p-i-n type and can be fabricated for front and/or backside (i.e., top and/or bottom) illumination. Additionally, the present invention is also directed at methods of making and using such devices, and to systems and modules (e.g., solar panels) employing such devices.

Abstract translation: 在一些实施例中，本发明涉及包含硅（Si）纳米线作为有源PV元件的光伏（PV）器件，其中这种器件通常是薄膜Si太阳能电池。 通常，这种太阳能电池是p-i-n型，并且可以制造用于正面和/或背面（即，顶部和/或底部）照明。 此外，本发明还涉及制造和使用这种装置以及采用这种装置的系统和模块（例如，太阳能电池板）的方法。

公开(公告)号：US07786469B2

公开(公告)日：2010-08-31

申请号：US12236480

申请日：2008-09-23

Applicant: Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

Inventor： Jer-Shen Maa ,  Jinke Tang ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Sheng Teng Hsu

IPC: H01L31/00

CPC classification number: H01L31/035254 ,  B82Y20/00 ,  H01L27/14649 ,  H01L31/028 ,  H01L31/101 ,  H01L31/1804 ,  Y02P70/521

Abstract: A silicon/germanium (SiGe) superlattice thermal sensor is provided with a corresponding fabrication method. The method forms an active CMOS device in a first Si substrate, and a SiGe superlattice structure on a second Si-on-insulator (SOI) substrate. The first substrate is bonded to the second substrate, forming a bonded substrate. An electrical connection is formed between the SiGe superlattice structure and the CMOS device, and a cavity is formed between the SiGe superlattice structure and the bonded substrate.

Abstract translation: 硅/锗（SiGe）超晶格热传感器具有相应的制造方法。 该方法在第一Si衬底中形成有源CMOS器件，并在第二绝缘体上（SOI）衬底上形成SiGe超晶格结构。 第一基板与第二基板接合，形成接合基板。 在SiGe超晶格结构和CMOS器件之间形成电连接，并且在SiGe超晶格结构和键合衬底之间形成空穴。