公开(公告)号：US20230096400A1

公开(公告)日：2023-03-30

申请号：US17485382

申请日：2021-09-25

Applicant: Xilinx, Inc.

Inventor： Sai Lalith Chaitanya Ambatipudi ,  Vamsi Krishna Nalluri ,  Sandeep Jayant Sathe ,  Chaithanya Dudha ,  Krishna Kishore Bhagavatula

IPC: G06F7/50

Abstract: An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in the comparison. The system includes an adder circuit configured to generate a sum of the indication values for each comparison value and a memory configured to maintain counts corresponding to the comparison values. The counts are updated by the respective sums. The system includes a threshold detection circuit configured to determine, for the dataset, a threshold value or threshold range based on the counts read from the memory.

公开(公告)号：US10678983B1

公开(公告)日：2020-06-09

申请号：US15987372

申请日：2018-05-23

Applicant: Xilinx, Inc.

Inventor： Shangzhi Sun ,  Chaithanya Dudha ,  Bing Tian ,  Ashish Sirasao

IPC: G06F30/3312 ,  G06F30/30 ,  G06F111/20 ,  G06F119/12

Abstract: Local retiming for a circuit design includes determining, using computer hardware, a load of a synchronous circuit element within the circuit design tagged for forward retiming, traversing, using the computer hardware, each input of the load backward through the circuit design until a sequential circuit element or a primary input is reached, and adding, using the computer hardware, each synchronous circuit element encountered in the traversing to a forward retiming list. In response to determining that forward retiming criteria is met for the forward retiming list, the computer hardware modifies the circuit design by creating a new synchronous circuit element at an output of the load.

公开(公告)号：US10289786B1

公开(公告)日：2019-05-14

申请号：US15634016

申请日：2017-06-27

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Shangzhi Sun ,  Ashish Sirasao ,  Nithin Kumar Guggilla

IPC: G06F17/50

Abstract: Reducing latency of a circuit design can include determining, using a processor, a set of sequential circuit elements of a circuit design that meets a condition for removal from the circuit design, wherein the condition is dependent upon a target technology process and a target operating frequency. Using the processor, a feasible cut for a selected sequential circuit element of the set is determined. The selected sequential circuit element and each other sequential circuit element of the set that is part of the cut is removed from the circuit design using the processor.

公开(公告)号：US11842168B2

公开(公告)日：2023-12-12

申请号：US17485382

申请日：2021-09-25

Applicant: Xilinx, Inc.

Inventor： Sai Lalith Chaitanya Ambatipudi ,  Vamsi Krishna Nalluri ,  Sandeep Jayant Sathe ,  Chaithanya Dudha ,  Krishna Kishore Bhagavatula

IPC: G06F7/50 ,  G06F7/02 ,  G06F17/18

CPC classification number: G06F7/50 ,  G06F7/026 ,  G06F17/18

Abstract: An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in the comparison. The system includes an adder circuit configured to generate a sum of the indication values for each comparison value and a memory configured to maintain counts corresponding to the comparison values. The counts are updated by the respective sums. The system includes a threshold detection circuit configured to determine, for the dataset, a threshold value or threshold range based on the counts read from the memory.

公开(公告)号：US11429769B1

公开(公告)日：2022-08-30

申请号：US17085838

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Pradip Kar ,  Nithin Kumar Guggilla ,  Chaithanya Dudha ,  Satyaprakash Pareek

IPC: G06F30/327 ,  G06F30/33 ,  G06F30/398 ,  G11C7/00 ,  G11B5/00 ,  G06F30/343

Abstract: Implementing a hardware description language (HDL) memory includes determining, using computer hardware, a width and a depth of the HDL memory specified as an HDL module for implementation in an integrated circuit (IC), partitioning, using the computer hardware, the HDL memory into a plurality of super slices corresponding to columns and the plurality of super slices into a plurality of super tiles arranged in rows. A heterogeneous memory array may be generated, using the computer hardware. The heterogeneous memory array is formed of different types of memory primitives of the IC. Input and output circuitry configured to access the heterogeneous memory array can be generated using the computer hardware.

公开(公告)号：US11188697B1

公开(公告)日：2021-11-30

申请号：US17141983

申请日：2021-01-05

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Rajeev Patwari ,  Nithin Kumar Guggilla ,  Ashish Sirasao ,  Krishna Garlapati

IPC: G06F30/333 ,  G06F30/343 ,  G06F30/3308 ,  G06F30/398 ,  G06F11/00 ,  G06F9/34 ,  G06F9/26 ,  G06F13/00 ,  G01R31/28 ,  G11C7/10 ,  G11C29/04 ,  G11B27/36 ,  G11B7/00 ,  G11B11/00 ,  H01L21/00 ,  G06F11/32 ,  G06F12/00

Abstract: Determining on-chip memory access patterns can include modifying a circuit design to include a profiler circuit for a random-access memory (RAM) of the circuit design, wherein the profiler circuit is configured to monitor an address bus of the RAM, and modifying the circuit design to include a debug circuit connected to the profiler circuit. Usage data for the RAM can be generated by detecting, using the profiler circuit, addresses of the RAM accessed during a test of the circuit design, as implemented in an integrated circuit. The usage data for the RAM can be output using the debug circuit.

公开(公告)号：US10990736B1

公开(公告)日：2021-04-27

申请号：US16821465

申请日：2020-03-17

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Satyaprakash Pareek ,  Krishna Garlapati ,  Ashish Sirasao

IPC: G06F30/30 ,  G06F30/337 ,  G06F30/327 ,  G03F1/70 ,  G06F30/31 ,  G06F119/12

Abstract: Implementing a circuit design can include detecting, using computer hardware, a re-convergent section of a circuit design, masking, using the computer hardware, a sequential circuit element of the re-convergent section located between a start and an end of the re-convergent section, and performing, using the computer hardware, an optimization operation on combinatorial logic of the re-convergent section to create optimized combinatorial logic. Using the computer hardware, the optimized combinatorial logic of the re-convergent section can be mapped. Further, the re-convergent section can be modified subsequent to the mapping to match timing of the re-convergent section prior to the masking.

公开(公告)号：US20180075172A1

公开(公告)日：2018-03-15

申请号：US15266827

申请日：2016-09-15

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Krishna Garlapati

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F1/32 ,  G06F17/5045 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.