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    Integrated circuit pre-boot metadata transfer
    11.
    发明授权
    Integrated circuit pre-boot metadata transfer 有权
    集成电路预引导元数据传输

    公开(公告)号：US09323876B1

    公开(公告)日：2016-04-26

    申请号：US14552321

    申请日：2014-11-24

    Applicant: Xilinx, Inc.

    Inventor： Patrick Lysaght ,  Yi-Hua E. Yang ,  Paul R. Schumacher ,  Graham F. Schelle

    IPC: G06F17/50 ,  G06F9/445

    CPC classification number: G06F8/65 ,  G06F17/5054

    Abstract: Pre-boot metadata transfer may include loading a first configuration bitstream into a programmable integrated circuit (IC), wherein the first configuration bitstream includes a first circuit design and metadata for a second circuit design. The metadata may be stored within a memory of the programmable IC. A configuration bitstream load condition may be detected and, responsive to the configuration bitstream load condition, a second configuration bitstream may be loaded into the programmable IC. The second configuration bitstream includes a second circuit design.

    Abstract translation: 预引导元数据传输可以包括将第一配置比特流加载到可编程集成电路（IC）中，其中第一配置比特流包括用于第二电路设计的第一电路设计和元数据。 元数据可以存储在可编程IC的存储器中。 可以检测配置比特流加载条件，并且响应于配置比特流加载条件，可以将第二配置比特流加载到可编程IC中。 第二配置比特流包括第二电路设计。

    System design flow with runtime customizable circuits
    13.
    发明授权
    System design flow with runtime customizable circuits 有权

    公开(公告)号：US10691856B1

    公开(公告)日：2020-06-23

    申请号：US15943519

    申请日：2018-04-02

    Applicant: Xilinx, Inc.

    Inventor： Patrick Lysaght ,  Graham F. Schelle

    IPC: G06F30/34 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398

    Abstract: A computer-implemented design flow can include, within a circuit design for an integrated circuit, determining a portion of the circuit design that is a candidate for implementation as a runtime customizable circuit and determining implementation options for the runtime customizable circuit. The design flow can also include generating, using computer hardware, a description of the circuit design using the runtime customizable circuit to implement the portion of the circuit design and generating, using the computer hardware, program code for an embedded processor coupled to an implementation of the runtime customizable circuit within the integrated circuit. The program code is usable by the embedded processor to parameterize the runtime customizable circuit to create a specific instance of the runtime customizable circuit.

    Runtime adaptive generator circuit
    14.
    发明授权
    Runtime adaptive generator circuit 有权

    公开(公告)号：US10289093B1

    公开(公告)日：2019-05-14

    申请号：US15850659

    申请日：2017-12-21

    Applicant: Xilinx, Inc.

    Inventor： Patrick Lysaght ,  Parimal Patel ,  Yun Qu ,  Graham F. Schelle

    IPC: G06F7/38 ,  H03K19/173 ,  G05B19/045 ,  G05B19/042

    Abstract: A system can include a finite state machine generator implemented in programmable circuitry of an integrated circuit. The finite state machine generator is parameterizable to implement different finite state machines at runtime of the integrated circuit. The system can include a processor configured to execute program code. The processor is configured to provide first parameterization data to the finite state machine generator at runtime of the integrated circuit. The first parameterization data specifies a first finite state machine and the finite state machine generator implements the first finite state machine in response to receiving the first parameterization data from the processor.

    SYSTEM-ON-CHIP INTELLECTUAL PROPERTY BLOCK DISCOVERY
    17.
    发明申请
    SYSTEM-ON-CHIP INTELLECTUAL PROPERTY BLOCK DISCOVERY 有权
    系统芯片知识产权发现

    公开(公告)号：US20160026742A1

    公开(公告)日：2016-01-28

    申请号：US14338155

    申请日：2014-07-22

    Applicant: Xilinx, Inc.

    Inventor： Graham F. Schelle ,  Paul R. Schumacher ,  Adrian M. Hernandez

    IPC: G06F17/50 ,  H03K19/177 ,  G11C7/10

    CPC classification number: G06F17/5068 ,  G06F17/5054 ,  G06F2217/66 ,  G11C5/025 ,  H03K19/17728

    Abstract: An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks implemented within the IC from the records of the memory map responsive to the first request. The bridge circuit is configured to send the list to the external system.

    Abstract translation: 集成电路（IC）包括被配置为从外部系统接收第一请求的桥接电路，耦合到桥接电路并被配置为处理从桥接电路接收的第一请求的发现电路以及耦合到发现的存储器映射 电路。 存储器映射存储在IC内实现的多个知识产权（IP）块中的每一个的记录。 发现电路被配置为响应于第一请求从存储器映射的记录生成在IC内实现的IP块的列表。 桥接电路配置为将列表发送到外部系统。

    Active interrupt handler performance monitoring in microprocessors
    18.
    发明授权
    Active interrupt handler performance monitoring in microprocessors 有权

    公开(公告)号：US10282326B1

    公开(公告)日：2019-05-07

    申请号：US14527659

    申请日：2014-10-29

    Applicant: Xilinx, Inc.

    Inventor： Yi-Hua E. Yang ,  Patrick Lysaght ,  Austin H. Lesea ,  Graham F. Schelle ,  Paul R. Schumacher

    IPC: G06F13/24 ,  G06F13/26

    Abstract: An integrated circuit is provided for obtaining interrupt performance metrics. The integrated circuit includes a microprocessor executing an interrupt service routing monitoring framework that includes an interrupt handler and an application programming interface. The interrupt handler executes in response to a trigger condition and obtains timing data that includes at least one sample of a value of a timing logic according to a sampling schedule. The API exposes interrupt configuration functionality for registering the interrupt handler with a supervisory program and for configuring the interrupt handler to obtain the timing data.

    Designing a system for a programmable system-on-chip using performance characterization techniques
    19.
    发明授权
    Designing a system for a programmable system-on-chip using performance characterization techniques 有权

    公开(公告)号：US09665683B1

    公开(公告)日：2017-05-30

    申请号：US14921674

    申请日：2015-10-23

    Applicant: Xilinx, Inc.

    Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Patrick Lysaght

    IPC: G06F17/50 ,  G06F9/455

    CPC classification number: G06F17/5054

    Abstract: An example method of implementing a system design for a programmable system-on-chip (SOC) having a processing system and programmable logic includes receiving a description of performance objectives for the system design. The method further includes accessing a characterization database that relates parameter settings of the processing system to performance under different traffic profiles as generated by an emulation system comprising the processing system and one or more circuit blocks implemented in the programmable logic. The method further includes obtaining a parameter set from the characterization database based on the description of the performance objectives. The method further includes generating a parameter image for setting registers of the processing system based on the parameter set.

    Methods and circuits for testing partial circuit designs
    20.
    发明授权
    Methods and circuits for testing partial circuit designs 有权
    用于测试部分电路设计的方法和电路

    公开(公告)号：US09581643B1

    公开(公告)日：2017-02-28

    申请号：US14924131

    申请日：2015-10-27

    Applicant: Xilinx, Inc.

    Inventor： Graham F. Schelle ,  Yi-Hua E. Yang ,  Paul R. Schumacher ,  Patrick Lysaght

    IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

    CPC classification number: G06F17/5022

    Abstract: Methods and circuits are disclosed for testing a partial circuit design including circuit modules having a set of ports configured to be driven by signals from ports of one or more circuits omitted from the partial circuit. The set of ports are identified by identifying ports that are not connected by a net to another port or input/output (I/O) pin in the circuit design and that form inputs to slave circuits in the circuit modules. A traffic generator circuit is added to the partial design to form a test circuit design. The traffic generator circuit is configured to provide to the set of ports respective input data signals having a pattern consistent with master-to-slave communication. Operation of a test circuit design is modeled. A set of data signals generated by the circuit modules during the modeled operation of the test circuit design is captured and stored.

    Abstract translation: 公开了用于测试部分电路设计的方法和电路，其包括具有一组端口的电路模块，该端口被配置为由来自部分电路省略的一个或多个电路的端口的信号驱动。 通过识别端口不被网络连接到电路设计中的另一个端口或输入/输出（I / O）引脚，并在电路模块中形成输入到从电路的端口。 交通发电机电路被添加到部分设计中以形成测试电路设计。 业务发生器电路被配置为向该组端口提供具有与主从通信一致的模式的相应输入数据信号。 测试电路设计的运行被建模。 捕获并存储在测试电路设计的建模操作期间由电路模块产生的一组数据信号。

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