公开(公告)号：US09729170B1

公开(公告)日：2017-08-08

申请号：US15193635

申请日：2016-06-27

Applicant: Xilinx, Inc.

Inventor： Arianne B. Roldan ,  Hsung Jai Im

IPC: H03M9/00 ,  H04L27/04

CPC classification number: H03M9/00 ,  H04L27/04

Abstract: An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.

公开(公告)号：US20160341780A1

公开(公告)日：2016-11-24

申请号：US14717985

申请日：2015-05-20

Applicant: XILINX, INC.

Inventor： Scott D. McLeod ,  Hsung Jai Im ,  Stanley Y. Chen

IPC: G01R31/04 ,  H03K3/012 ,  H03K3/3568 ,  G01R31/28

CPC classification number: G01R31/041 ,  G01R31/2884 ,  G01R31/318572 ,  H03K3/012 ,  H03K3/3568 ,  H03K19/017527 ,  H03K19/018514 ,  H04L25/0272

Abstract: In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.

Abstract translation: 在一个示例中，驱动器电路包括被配置为被电流源偏置并包括差分输入和差分输出的差分晶体管对。 驱动器电路还包括耦合在节点对和差分输出之间的电阻器对，耦合在电压源和节点对之间的晶体管对以及耦合在节点对之间的桥式晶体管。 驱动器电路还包括一对三态电路元件，其具有相应的一对输入端口，相应的一对控制端口和相应的一对输出端口。 输出端口对分别耦合到节点对。 该对控制端口耦合到包括晶体管对的每个栅极和桥式晶体管的栅极的公共节点。

公开(公告)号：US11923857B1

公开(公告)日：2024-03-05

申请号：US18102066

申请日：2023-01-26

Applicant: XILINX, INC.

Inventor： Hongtao Zhang ,  Ankur Jain ,  Yanfei Chen ,  Ronan Sean Casey ,  Winson Lin ,  Hsung Jai Im

IPC: H03L7/08 ,  H03L7/099 ,  H03M1/82

CPC classification number: H03L7/0802 ,  H03L7/0991 ,  H03M1/82

Abstract: Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

公开(公告)号：US11177984B1

公开(公告)日：2021-11-16

申请号：US16889573

申请日：2020-06-01

Applicant: Xilinx, Inc.

Inventor： Kevin Zheng ,  Chuen-Huei Chou ,  Hsung Jai Im

IPC: H03H7/40 ,  H04L25/03 ,  H04L27/01 ,  H01L21/8238

Abstract: A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.

公开(公告)号：US09841455B2

公开(公告)日：2017-12-12

申请号：US14717985

申请日：2015-05-20

Applicant: Xilinx, Inc.

Inventor： Scott D. McLeod ,  Hsung Jai Im ,  Stanley Y. Chen

IPC: G01R31/04 ,  H03K3/012 ,  H03K3/3568 ,  G01R31/28 ,  G01R31/3185 ,  H03K19/0175 ,  H03K19/0185 ,  H04L25/02

CPC classification number: G01R31/041 ,  G01R31/2884 ,  G01R31/318572 ,  H03K3/012 ,  H03K3/3568 ,  H03K19/017527 ,  H03K19/018514 ,  H04L25/0272

Abstract: In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.