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    Communicating between data processing engines using shared memory
    11.
    发明授权
    Communicating between data processing engines using shared memory 有权

    公开(公告)号：US11379389B1

    公开(公告)日：2022-07-05

    申请号：US15944179

    申请日：2018-04-03

    Applicant: Xilinx, Inc.

    Inventor： Juan J. Noguera Serra ,  Goran H K Bilski ,  Baris Ozgul ,  Jan Langer

    IPC: G06F13/16 ,  G06F12/084 ,  G06F9/54 ,  G11C8/16 ,  G06F15/167

    Abstract: Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.

    Core for a data processing engine in an integrated circuit
    13.
    发明授权
    Core for a data processing engine in an integrated circuit 有权

    公开(公告)号：US10747531B1

    公开(公告)日：2020-08-18

    申请号：US15944315

    申请日：2018-04-03

    Applicant: Xilinx, Inc.

    Inventor： Jan Langer ,  Baris Ozgul ,  Juan J. Noguera Serra ,  Goran HK Bilski ,  Tim Tuan

    IPC: G06F9/302 ,  G06F7/57 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F7/499 ,  G06F15/80

    Abstract: An example core for a data processing engine (DPE) includes a register file, a processor, coupled to the register file. The processor includes a multiply-accumulate (MAC) circuit, and permute circuitry coupled between the register file and the MAC circuit, the permute circuitry configured to concatenate at least one pair of outputs of the register file to provide at least one input to the MAC circuit. The core further includes an instruction decoder, coupled to the processor, configured to decode a very large instruction word (VLIW) to set a plurality of parameters of the processor, the plurality of parameters including first parameters of the permute circuitry and second parameters of the MAC circuit.

    Multi-port stream switch for stream interconnect network
    18.
    发明授权
    Multi-port stream switch for stream interconnect network 有权

    公开(公告)号：US11323391B1

    公开(公告)日：2022-05-03

    申请号：US16833029

    申请日：2020-03-27

    Applicant: XILINX, INC.

    Inventor： Peter McColgan ,  David Clarke ,  Goran Hk Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Tim Tuan

    IPC: H04L12/935 ,  G06F13/28 ,  H04L49/00

    Abstract: Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.

    Data selection network for a data processing engine in an integrated circuit
    19.
    发明授权
    Data selection network for a data processing engine in an integrated circuit 有权

    公开(公告)号：US11061673B1

    公开(公告)日：2021-07-13

    申请号：US15944393

    申请日：2018-04-03

    Applicant: Xilinx, Inc.

    Inventor： Baris Ozgul ,  Jan Langer ,  Juan J. Noguera Serra ,  Goran H. K. Bilski ,  Richard L. Walke

    IPC: G06F9/30 ,  G06F17/16

    Abstract: An example core for data processing engine (DPE) includes a first register file configured to provide a first plurality of output lanes, a processor, coupled to the register file, including: a multiply-accumulate (MAC) circuit, and a first permute circuit coupled between the first register file and the MAC circuit. The first permute circuit is configured to generate a first vector by selecting a first set of output lanes from the first plurality of output lanes, and a second permute circuit coupled between the first register file and the MAC circuit. The second permute circuit is configured to generate a second vector by selecting a second set of output lanes from the first plurality of output lanes.

    Cascade streaming between data processing engines in an array
    20.
    发明授权
    Cascade streaming between data processing engines in an array 有权

    公开(公告)号：US11016822B1

    公开(公告)日：2021-05-25

    申请号：US15944578

    申请日：2018-04-03

    Applicant: Xilinx, Inc.

    Inventor： Goran H. K. Bilski ,  Juan J. Noguera Serra ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke

    IPC: G06F9/50 ,  G06F9/48

    Abstract: Examples herein describe techniques for communicating directly between cores in an array of data processing engines. In one embodiment, the array is a 2D array where each of the data processing engines includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the cores. Using the interconnect, however, can add latency when transmitting data between the cores. In the embodiments herein, the array includes core-to-core communication links that directly connect one core in the array to another core. The cores can use these communication links to bypass the interconnect and the memory module to transmit data directly.

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