公开(公告)号：US09639646B2

公开(公告)日：2017-05-02

申请号：US14338155

申请日：2014-07-22

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Paul R. Schumacher ,  Adrian M. Hernandez

IPC: G06F9/455 ,  G06F17/50 ,  H03K19/177 ,  G11C5/02

CPC classification number: G06F17/5068 ,  G06F17/5054 ,  G06F2217/66 ,  G11C5/025 ,  H03K19/17728

Abstract: An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks implemented within the IC from the records of the memory map responsive to the first request. The bridge circuit is configured to send the list to the external system.

公开(公告)号：US20160026742A1

公开(公告)日：2016-01-28

申请号：US14338155

申请日：2014-07-22

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Paul R. Schumacher ,  Adrian M. Hernandez

IPC: G06F17/50 ,  H03K19/177 ,  G11C7/10

CPC classification number: G06F17/5068 ,  G06F17/5054 ,  G06F2217/66 ,  G11C5/025 ,  H03K19/17728

Abstract: An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks implemented within the IC from the records of the memory map responsive to the first request. The bridge circuit is configured to send the list to the external system.

Abstract translation: 集成电路（IC）包括被配置为从外部系统接收第一请求的桥接电路，耦合到桥接电路并被配置为处理从桥接电路接收的第一请求的发现电路以及耦合到发现的存储器映射 电路。 存储器映射存储在IC内实现的多个知识产权（IP）块中的每一个的记录。 发现电路被配置为响应于第一请求从存储器映射的记录生成在IC内实现的IP块的列表。 桥接电路配置为将列表发送到外部系统。

公开(公告)号：US11816335B1

公开(公告)日：2023-11-14

申请号：US17660808

申请日：2022-04-26

Applicant: Xilinx, Inc.

Inventor： Sachin Kumawat ,  David K. Liddell ,  Paul R. Schumacher

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0673

Abstract: A system includes a first multi-port RAM storing an instruction table. The instruction table specifies a regular expression for application to a data stream and a second multi-port RAM configured to store a capture table having capture entries decodable for tracking position information for a sequence of characters matching a capture sub-expression of the regular expression. The system includes a regular expression engine processing the data stream to determine match states by tracking active states for the regular expression and priorities for the active states by storing the active states of the regular expression in a plurality of priority FIFO memories in decreasing priority order. The system includes a capture engine operating in coordination with the regular expression engine to determine character(s) of the data stream that match the capture sub-expression based on the active state being tracked and decoding the capture entries of the capture table.

公开(公告)号：US10282326B1

公开(公告)日：2019-05-07

申请号：US14527659

申请日：2014-10-29

Applicant: Xilinx, Inc.

Inventor： Yi-Hua E. Yang ,  Patrick Lysaght ,  Austin H. Lesea ,  Graham F. Schelle ,  Paul R. Schumacher

IPC: G06F13/24 ,  G06F13/26

Abstract: An integrated circuit is provided for obtaining interrupt performance metrics. The integrated circuit includes a microprocessor executing an interrupt service routing monitoring framework that includes an interrupt handler and an application programming interface. The interrupt handler executes in response to a trigger condition and obtains timing data that includes at least one sample of a value of a timing logic according to a sampling schedule. The API exposes interrupt configuration functionality for registering the interrupt handler with a supervisory program and for configuring the interrupt handler to obtain the timing data.

公开(公告)号：US09665683B1

公开(公告)日：2017-05-30

申请号：US14921674

申请日：2015-10-23

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Patrick Lysaght

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5054

Abstract: An example method of implementing a system design for a programmable system-on-chip (SOC) having a processing system and programmable logic includes receiving a description of performance objectives for the system design. The method further includes accessing a characterization database that relates parameter settings of the processing system to performance under different traffic profiles as generated by an emulation system comprising the processing system and one or more circuit blocks implemented in the programmable logic. The method further includes obtaining a parameter set from the characterization database based on the description of the performance objectives. The method further includes generating a parameter image for setting registers of the processing system based on the parameter set.

公开(公告)号：US09581643B1

公开(公告)日：2017-02-28

申请号：US14924131

申请日：2015-10-27

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Yi-Hua E. Yang ,  Paul R. Schumacher ,  Patrick Lysaght

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G06F17/5022

Abstract: Methods and circuits are disclosed for testing a partial circuit design including circuit modules having a set of ports configured to be driven by signals from ports of one or more circuits omitted from the partial circuit. The set of ports are identified by identifying ports that are not connected by a net to another port or input/output (I/O) pin in the circuit design and that form inputs to slave circuits in the circuit modules. A traffic generator circuit is added to the partial design to form a test circuit design. The traffic generator circuit is configured to provide to the set of ports respective input data signals having a pattern consistent with master-to-slave communication. Operation of a test circuit design is modeled. A set of data signals generated by the circuit modules during the modeled operation of the test circuit design is captured and stored.

Abstract translation: 公开了用于测试部分电路设计的方法和电路，其包括具有一组端口的电路模块，该端口被配置为由来自部分电路省略的一个或多个电路的端口的信号驱动。 通过识别端口不被网络连接到电路设计中的另一个端口或输入/输出（I / O）引脚，并在电路模块中形成输入到从电路的端口。 交通发电机电路被添加到部分设计中以形成测试电路设计。 业务发生器电路被配置为向该组端口提供具有与主从通信一致的模式的相应输入数据信号。 测试电路设计的运行被建模。 捕获并存储在测试电路设计的建模操作期间由电路模块产生的一组数据信号。

公开(公告)号：US09529946B1

公开(公告)日：2016-12-27

申请号：US13676035

申请日：2012-11-13

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Patrick Lysaght ,  Alan M. Frost

IPC: G06F17/50 ,  G06F11/26

CPC classification number: G06F17/5022 ,  G06F11/00 ,  G06F11/261 ,  G06F11/3062 ,  G06F11/3457 ,  G06F17/5027

Abstract: An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to consume a variable amount of power as specified by the first modeling data received via the first port.

Abstract translation: 集成电路可以包括可操作以执行程序代码和知识产权（IP）建模块的处理器。 IP建模块可以包括第一端口，IP建模块通过该第一端口接收第一建模数据，以及耦合到处理器的第二端口，第一IP建模块在仿真期间与处理器通信。 第一个IP建模块还可以包括一个电源仿真电路。 功率仿真电路被配置为消耗由经由第一端口接收的第一建模数据指定的可变量的功率。

公开(公告)号：US09058135B1

公开(公告)日：2015-06-16

申请号：US13674621

申请日：2012-11-12

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Graham F. Schelle

IPC: G06F1/12 ,  G11C7/22 ,  G06F1/14 ,  G06F5/06 ,  G06F1/10

CPC classification number: G06F1/12 ,  G06F1/10 ,  G06F1/14 ,  G06F5/06 ,  G11C7/22 ,  G11C7/222

Abstract: Testing a digital system includes calculating a first ratio of a first clock frequency for a first clock domain and a second clock frequency for a second clock domain different from the first clock domain using a processing device and calculating a first offset between a first timer in the first clock domain and a second timer in the second clock domain. Using an expression dependent upon the first offset and the first ratio, event data from at least one of the first clock domain or the second clock domain is converted to a common clock domain.

Abstract translation: 测试数字系统包括使用处理装置计算第一时钟频率的第一时钟频率和与第一时钟域不同的第二时钟域的第二时钟频率，并且计算第一时钟频率 第一时钟域和第二时钟域中的第二定时器。 使用依赖于第一偏移和第一比率的表达式，来自第一时钟域或第二时钟域中的至少一个的事件数据被转换为公共时钟域。

公开(公告)号：US10816600B1

公开(公告)日：2020-10-27

申请号：US15824789

申请日：2017-11-28

Applicant: Xilinx, Inc.

Inventor： David K. Liddell ,  Paul R. Schumacher

IPC: G01R31/3183 ,  G01R31/28 ,  G06F30/33 ,  G01R31/3193

Abstract: Protocol analysis can include simulating, using a processor, a circuit design including a protocol analyzer embedded therein. The protocol analyzer can be coupled to low-level signals of an interface of the circuit design. During the simulating, the protocol analyzer detects a transaction from the low-level signals received from the interface. Transaction data is generated by the protocol analyzer specifying the transaction. The transaction data is output from the protocol analyzer.

公开(公告)号：US10740210B1

公开(公告)日：2020-08-11

申请号：US15824631

申请日：2017-11-28

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Kumar Deepak ,  Roger Ng ,  David K. Liddell

IPC: G06F9/44 ,  G06F11/34 ,  G06F8/41 ,  G06F7/02 ,  G06F11/36 ,  G06F16/2458

Abstract: Tracing operation of a kernel can include comparing, using a processor, signals of a compiled kernel with a database including compiler generated signals for compute units to determine a list of the signals of the compiled kernel that match the compiler generated signals and generating trace data by emulating the compiled kernel using the processor. The trace data includes values for signals of the compiled kernel collected over time during the emulation. Operational data corresponding to individual compute units of the compiled kernel can be determined from values of the signals of the list within the trace data using the processor. The operational data can be displayed using the processor.