公开(公告)号：US10824434B1

公开(公告)日：2020-11-03

申请号：US16204991

申请日：2018-11-29

Applicant: Xilinx, Inc.

Inventor： Sean Settle ,  Ehsan Ghasemi ,  Ashish Sirasao ,  Ralph D. Wittig

IPC: G06F9/38 ,  G06F9/30

Abstract: Examples described herein relate to dynamically structured single instruction, multiple data (SIMD) instructions, and systems and circuits implementing such dynamically structured SIMD instructions. An example is a method for processing data. A first SIMD structure is determined by a processor. A characteristic of the first SIMD structure is altered by the processor to obtain a second SIMD structure. An indication of the second SIMD structure is communicated from the processor to a numerical engine. Data is packed by the numerical engine into an SIMD instruction according to the second SIMD structure. The SIMD instruction is transmitted from the numerical engine.

公开(公告)号：US10747690B2

公开(公告)日：2020-08-18

申请号：US15944307

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran H K Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  H04L12/933

Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

公开(公告)号：US20190303311A1

公开(公告)日：2019-10-03

申请号：US15944307

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran HK Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F13/16 ,  G06F13/40

Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

公开(公告)号：US09846660B2

公开(公告)日：2017-12-19

申请号：US14539985

申请日：2014-11-12

Applicant: Xilinx, Inc.

Inventor： Henry E. Styles ,  Jeffrey M. Fifield ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Sonal Santan ,  Devadas Varma ,  Fernando J. Martinez Vallina ,  Sheng Zhou ,  Charles Kwok-Wah Lo

IPC: G06F13/12 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1689 ,  G06F13/28

Abstract: An integrated circuit (IC) includes a first region being static and providing an interface between the IC and a host processor. The first region includes a first interconnect circuit block having a first master interface and a second interconnect circuit block having a first slave interface. The IC includes a second region coupled to the first region. The second region implements a kernel of a heterogeneous, multiprocessor design and includes a slave interface coupled to the first master interface of the first interconnect circuit block and configured to receive commands from the host processor. The second region also includes a master interface coupled the first slave interface of the second interconnect circuit block, wherein the master interface of the second region is a master for a memory controller.

公开(公告)号：US11281440B1

公开(公告)日：2022-03-22

申请号：US17065433

申请日：2020-10-07

Applicant: XILINX, INC.

Inventor： Chia-Jui Hsu ,  Shail Aditya Gupta ,  Samuel R. Bayliss ,  Philip B. James-Roxby ,  Ralph D. Wittig ,  Vinod Kathail

IPC: G06F8/41 ,  G06F11/34 ,  G06F9/54 ,  G06F16/901

Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

公开(公告)号：US20200371761A1

公开(公告)日：2020-11-26

申请号：US16420831

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Akella Sastry

IPC: G06F8/41 ,  G06F9/54 ,  G06F16/901 ,  G06F15/78

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

公开(公告)号：US20190303033A1

公开(公告)日：2019-10-03

申请号：US15944160

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran HK Bilski ,  Jan Langer ,  Baris Ozgul ,  Tim Tuan ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Christopher H. Dick

IPC: G06F3/06

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

公开(公告)号：US09218443B1

公开(公告)日：2015-12-22

申请号：US14539975

申请日：2014-11-12

Applicant: Xilinx, Inc.

Inventor： Henry E. Styles ,  Jeffrey M. Fifield ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Sonal Santan ,  Devadas Varma ,  Fernando J. Martinez Vallina ,  Sheng Zhou ,  Charles Kwah-Wah Lo

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F8/451

Abstract: OpenCL program compilation may include generating, using a processor, a register transfer level (RTL) description of a first kernel of a heterogeneous, multiprocessor design and integrating the RTL description of the first kernel with a base platform circuit design. The base platform circuit design provides a static interface within a programmable integrated circuit to a host of the heterogeneous, multiprocessor design. A first configuration bitstream may be generated from the RTL description of the first kernel using the processor. The first configuration bitstream specifies a hardware implementation of the first kernel and supporting data for the configuration bitstream. The first configuration bitstream and the supporting data may be included within a binary container.

Abstract translation: OpenCL程序编译可以包括使用处理器来生成异构多处理器设计的第一内核的寄存器传送级（RTL）描述，并将第一内核的RTL描述与基本平台电路设计集成。 基础平台电路设计为可编程集成电路内的静态接口提供了异构多处理器设计的主机。 可以使用处理器从第一内核的RTL描述生成第一配置比特流。 第一配置比特流指定第一内核的硬件实现和配置比特流的支持数据。 第一配置比特流和支持数据可以包括在二进制容器内。