公开(公告)号：US09805152B1

公开(公告)日：2017-10-31

申请号：US15046147

申请日：2016-02-17

Applicant: Xilinx, Inc.

Inventor： Jorge E. Carrillo ,  Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Hua Sun

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.

公开(公告)号：US09652570B1

公开(公告)日：2017-05-16

申请号：US14845100

申请日：2015-09-03

Applicant: Xilinx, Inc.

Inventor： Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Jorge E. Carrillo ,  Hua Sun ,  Tom Shui ,  Yogesh L. Chobe

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.

公开(公告)号：US12159057B2

公开(公告)日：2024-12-03

申请号：US17934153

申请日：2022-09-21

Applicant: Xilinx, Inc.

Inventor： Chia-Jui Hsu ,  Mukund Sivaraman ,  Vinod K. Kathail

IPC: G06F3/06

Abstract: Implementing data flows of an application across a memory hierarchy of a data processing array includes receiving a data flow graph specifying an application for execution on the data processing array. A plurality of buffer objects corresponding to a plurality of different levels of the memory hierarchy of the data processing array and an external memory are identified. The plurality of buffer objects specify data flows. Buffer object parameters are determined. The buffer object parameters define properties of the data flows. Data that configures the data processing array to implement the data flows among the plurality of different levels of the memory hierarchy and the external memory is generated based on the plurality of buffer objects and the buffer object parameters.

公开(公告)号：US20240094944A1

公开(公告)日：2024-03-21

申请号：US17934153

申请日：2022-09-21

Applicant: Xilinx, Inc.

Inventor： Chia-Jui Hsu ,  Mukund Sivaraman ,  Vinod K. Kathail

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0622 ,  G06F3/0683

Abstract: Implementing data flows of an application across a memory hierarchy of a data processing array includes receiving a data flow graph specifying an application for execution on the data processing array. A plurality of buffer objects corresponding to a plurality of different levels of the memory hierarchy of the data processing array and an external memory are identified. The plurality of buffer objects specify data flows. Buffer object parameters are determined. The buffer object parameters define properties of the data flows. Data that configures the data processing array to implement the data flows among the plurality of different levels of the memory hierarchy and the external memory is generated based on the plurality of buffer objects and the buffer object parameters.

公开(公告)号：US20200372123A1

公开(公告)日：2020-11-26

申请号：US16421443

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Srinivas Beeravolu ,  Dinesh K. Monga ,  Pradip Jha ,  Vishal Suthar ,  Vinod K. Kathail ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F17/50

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US20200371761A1

公开(公告)日：2020-11-26

申请号：US16420831

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Akella Sastry

IPC: G06F8/41 ,  G06F9/54 ,  G06F16/901 ,  G06F15/78

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

公开(公告)号：US09880966B1

公开(公告)日：2018-01-30

申请号：US14845127

申请日：2015-09-03

Applicant: Xilinx, Inc.

Inventor： L. James Hwang ,  Vinod K. Kathail ,  Sundararajarao Mohan ,  Jorge E. Carrillo ,  Hua Sun

IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00

CPC classification number: G06F13/4256 ,  G06F13/24 ,  G06F13/4022

Abstract: Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

公开(公告)号：US09223921B1

公开(公告)日：2015-12-29

申请号：US14540854

申请日：2014-11-13

Applicant: Xilinx, Inc.

Inventor： Jorge E. Carrillo ,  L. James Hwang ,  Hua Sun ,  Sundararajarao Mohan ,  Vinod K. Kathail

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F8/447

Abstract: In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.

Abstract translation: 在一个示例实现中，提供了一种用于编译HLL源文件的方法。 HLL源文件检查了对硬件库中指定的硬件实现的一组硬件加速功能的函数调用。 对于硬件加速功能的每个HLL函数调用，从硬件库检索电路设计。 电路设计规定了硬件加速功能的硬件实现。 HLL接口代码配置为与硬件通信实现硬件加速功能也被生成。 HLL源文件中的硬件加速功能的HLL函数调用将替换为生成的接口代码。 HLL源文件被编译成在可编程IC的处理器上生成可执行的程序。 生成配置数据，其实现在可编程IC的可编程电路上检索的电路设计。

公开(公告)号：US08762916B1

公开(公告)日：2014-06-24

申请号：US13776318

申请日：2013-02-25

Applicant: Xilinx, Inc.

Inventor： Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Hua Sun

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5054

Abstract: A method of automatically developing a data transfer network includes determining, using a processor, a plurality of data transfers of a function of a circuit design marked for hardware acceleration within a target integrated circuit. The circuit design is specified in a high level programming language, and at least one other function of the circuit design remains executable by a microprocessor of the target integrated circuit. Each of the plurality of data transfers is characterized. Each of the plurality of data transfers is correlated with resources of the target integrated circuit. A programmatic description of a data transfer network is generated for the circuit design. The data transfer network connects the hardware accelerator and the microprocessor according to the characterizing and the correlating.

Abstract translation: 自动开发数据传输网络的方法包括：使用处理器来确定在目标集成电路内标记为硬件加速的电路设计的功能的多个数据传输。 电路设计以高级编程语言指定，并且电路设计的至少一个其他功能仍然可以由目标集成电路的微处理器执行。 多个数据传输中的每一个都被表征。 多个数据传输中的每一个与目标集成电路的资源相关。 为电路设计生成数据传输网络的编程描述。 数据传输网络根据特征和相关性连接硬件加速器和微处理器。