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11.发明授权公开(公告)号：US11114458B2
公开(公告)日：2021-09-07
申请号：US16670594
申请日：2019-10-31
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
IPC分类号： H01L27/11565 , H01L27/11582 , H01L27/1157
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The 3D memory device also includes a plurality of channel structures extending vertically through the memory stack into the substrate. The 3D memory device further includes at least one slit structure extending vertically and laterally in the memory stack and dividing a plurality of memory cells into at least one memory block, the at least one slit structure each including a plurality of slit openings and a support structure between adjacent slit openings. The support structure may be in contact with adjacent memory blocks and contacting the substrate.
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公开(公告)号：US11094713B2
公开(公告)日：2021-08-17
申请号：US16689513
申请日：2019-11-20
发明人： Qingqing Wang , Wei Xu , Pan Huang , Ping Yan , Zongliang Huo , Wenbin Zhou
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L23/528
摘要： A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved conductor layers and insulating layers. The 3D memory device also includes channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes first and second source contacts separated by a support structure. The source structure also includes an adhesion layer. At least a portion of the adhesion layer is between the first and second source contacts and conductively connects the first and second source contacts.
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公开(公告)号：US20210183878A1
公开(公告)日：2021-06-17
申请号：US17185963
申请日：2021-02-26
发明人： Wenxiang Xu , Wei Xu , Pan Huang , Ping Yan , Zongliang Huo , Wenbin Zhou , Ji Xia
IPC分类号： H01L27/11565 , H01L21/02 , H01L21/311 , H01L21/768 , H01L27/11582
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes the following operations. A cut structure is first formed in a stack structure. The stack structure includes interleaved initial sacrificial layers and initial insulating layers. A patterned cap material layer is formed over the stack structure. The patterned cap material layer includes an opening over the cut structure. Portions of the stack structure and the patterned cap material layer adjacent to the opening are removed to form a slit structure and an initial support structure. The initial support structure divides the slit structure into slit openings. Conductor portions are formed through the plurality of slit openings to form a support structure. A source contact is formed in each slit opening. A connection layer is formed over the source contact in each slit opening and over the support structure.
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公开(公告)号：US20210104540A1
公开(公告)日：2021-04-08
申请号：US17100841
申请日：2020-11-21
发明人： Bo Xu , Ping Yan , Chuan Yang , Jing Gao , Zongliang Huo , Lu Zhang
IPC分类号： H01L27/11582 , H01L21/02 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/11565 , H01L29/10
摘要： Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.
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公开(公告)号：US20210050366A1
公开(公告)日：2021-02-18
申请号：US16655157
申请日：2019-10-16
发明人： Pan Huang , Wei Xu , Ping Yan , Wenxiang Xu , Zongliang Huo , Wenbin Zhou , Ji Xia
IPC分类号： H01L27/11582 , H01L21/768 , H01L27/11565 , H01L21/02 , H01L21/311
摘要： Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack over a substrate, a plurality of channel structures, and a source structure. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure extend in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. At least two of the plurality of source contacts are in contact with and conductively connected to one another.
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公开(公告)号：US10727245B2
公开(公告)日：2020-07-28
申请号：US16046818
申请日：2018-07-26
发明人： Qiang Xu , Zhiliang Xia , Ping Yan , Guangji Li , Zongliang Huo
IPC分类号： H01L27/11578 , H01L27/11575 , H01L21/762 , H01L27/11582 , H01L27/11565 , H01L27/1157
摘要： The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
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公开(公告)号：US11758723B2
公开(公告)日：2023-09-12
申请号：US17148551
申请日：2021-01-13
发明人： Qingqing Wang , Wei Xu , Pan Huang , Ping Yan , Zongliang Huo , Wenbin Zhou
IPC分类号： H10B43/27 , H01L23/528 , H10B43/10 , H10B43/35
CPC分类号： H10B43/27 , H01L23/5283 , H10B43/10 , H10B43/35
摘要： A method for forming a three-dimensional (3D) memory device includes forming a cut structure in a stack structure. The stack structure includes interleaved a plurality of initial sacrificial layers and a plurality of initial insulating layers. The method also includes removing portions of the stack structure adjacent to the cut structure to form a slit structure and an initial support structure. The initial support structure divides the slit structure into a plurality of slit openings. The method further includes forming a plurality of conductor portions in the initial support structure through the plurality of slit openings. The method also includes forming a source contact in each of the plurality of slit openings. The method also includes removing portions of the initial support structure to form a support structure. The support structure includes an adhesion portion extending through the support structure. In addition, the method includes forming an adhesion layer over the source contact in each of the plurality of slit openings. At least two adhesion layers are conductively connected to the adhesion portion extending through the support structure.
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公开(公告)号：US11729971B2
公开(公告)日：2023-08-15
申请号：US17645102
申请日：2021-12-20
发明人： Qiang Xu , Zhiliang Xia , Ping Yan , Guangji Li , Zongliang Huo
摘要： The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.
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19.发明授权公开(公告)号：US11716850B2
公开(公告)日：2023-08-01
申请号：US17170872
申请日：2021-02-08
发明人： Zongliang Huo , Haohao Yang , Wei Xu , Ping Yan , Pan Huang , Wenbin Zhou
IPC分类号： H01L27/11582 , H10B43/27 , H10B43/10 , H10B43/35
摘要： A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions. The method also includes forming channel structures extending vertically through the dielectric stack, replacing the sacrificial layers and sacrificial portions with conductor layers and conductor portions through the at least one slit structure, and forming a source structure in each slit structure. The source structure may include an insulating spacer in each slit opening and a source contact in a respective insulating spacer.
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公开(公告)号：US11594552B2
公开(公告)日：2023-02-28
申请号：US17100841
申请日：2020-11-21
发明人： Bo Xu , Ping Yan , Chuan Yang , Jing Gao , Zongliang Huo , Lu Zhang
IPC分类号： H01L29/51 , H01L27/11582 , H01L21/02 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/11565 , H01L29/10 , H01L21/28 , H01L21/768
摘要： Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.
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