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    Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells
    11.
    发明授权
    Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
    具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件

    公开(公告)号：US5557568A

    公开(公告)日：1996-09-17

    申请号：US427265

    申请日：1995-04-24

    申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

    发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

    IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

    摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

    摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，晶体管对位线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 一种数据设定电路，用于在触发电路的第一和第二信号节点之一连接到预定电位，当位线在验证模式下处于充电电位时，从而将触发器电路设置在第二状态，而与 在验证模式之前的状态。

    Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells
    12.
    发明授权
    Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
    具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件

    公开(公告)号：US5452249A

    公开(公告)日：1995-09-19

    申请号：US210434

    申请日：1994-03-21

    申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

    发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

    IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

    摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor changes the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

    摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，并且晶体管改变位线。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点中的一个连接到预定电位，从而将触发电路设置为第二状态 在验证模式之前的状态。

    Semiconductor memory device with program/erase verification
    15.
    发明授权
    Semiconductor memory device with program/erase verification 失效
    具有编程/擦除验证的半导体存储器件

    公开(公告)号：US5761122A

    公开(公告)日：1998-06-02

    申请号：US749673

    申请日：1996-11-15

    申请人： Hiroshi Nakamura ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Keniti Imamiya

    发明人： Hiroshi Nakamura ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Keniti Imamiya

    IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： G11C16/3477 ,  G11C16/10 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3486 ,  G11C7/00

    摘要： A semiconductor memory device includes a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each, of which is arranged at one end of at least one bit line connected to the memory cell array and for latching programming data, a control section for judging whether all of a plurality of latched data included in date latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, a section for detecting potentials of the plurality of the first nodes and for judging whether all data latched by the latch circuits are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and a section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, are the same as the first data or not.

    摘要翻译： 半导体存储器件包括半导体衬底，具有存储单元的存储单元阵列，每个存储单元存储矩阵形成在半导体衬底上的数据，多个数据锁存电路，每个数据锁存电路至少布置在一端 连接到存储单元阵列的一位线和用于锁存编程数据的控制部分，用于判断包括在由多个数据锁存电路构成的日期锁存组中的多个锁存数据是否与第一数据相同的控制部分 并且用于根据判断结果控制多个第一节点的电位变化，用于检测多个第一节点的电位的部分和用于判断由锁存电路锁存的所有数据是否与第一数据相同， 用于根据判断结果控制多个第二节点的电位，以及用于检测多个第二节点和fo的电位的部分 r输出由数据锁存电路锁存的所有数据是否与第一数据相同的判断结果。

    Semiconductor memory device
    18.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5610859A

    公开(公告)日：1997-03-11

    申请号：US404572

    申请日：1995-03-15

    申请人： Hiroshi Nakamura ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Keniti Imamiya

    发明人： Hiroshi Nakamura ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Keniti Imamiya

    IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C11/34

    CPC分类号： G11C16/3477 ,  G11C16/10 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3486 ,  G11C7/00

    摘要： A semiconductor memory device according to the invention comprises a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each of which is arranged a one end of at least one bit line connected to the memory cell array and for latching programming data, control section for judging whether all of a plurality of latched data included in data latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, where there is one first node corresponding to each data latch circuit group, section for detecting potentials of the plurality of the first nodes corresponding to the plurality of data latch circuit groups, judging whether all data latched by the latch circuits includes in the plurality of latch circuit groups are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, which are included in the plurality of the data latch circuit groups, are the same as the first data or not.

    摘要翻译： 根据本发明的半导体存储器件包括半导体衬底，具有存储单元的存储单元阵列，每个存储器单元存储矩阵形成在半导体衬底上的数据，多个数据锁存电路，每个数据锁存电路布置成一端 连接到存储单元阵列的至少一个位线和用于锁存编程数据的控制部分，用于判断包括在由多个数据锁存电路构成的数据锁存器组中的多个锁存数据是否与第一数据相同 并且用于根据判断结果控制多个第一节点的电位，其中存在对应于每个数据锁存电路组的一个第一节点，用于检测对应于多个第一节点的多个第一节点的电位的部分 的数据锁存电路组，判断由锁存电路锁存的所有数据是否包含在多个锁存电路组中是相同的 第一数据和用于根据判断结果控制多个第二节点的电位的变化，以及用于检测多个第二节点的电位的部分，并且用于输出由数据锁存电路锁存的所有数据的判断结果， 包含在多个数据锁存电路组中的数据与第一数据相同。